📄 counter.rpt
字号:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\kkk\counter.rpt
counter
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 6/ 96( 6%) 4/ 48( 8%) 0/ 48( 0%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\kkk\counter.rpt
counter
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 7 clock
Device-Specific Information: f:\kkk\counter.rpt
counter
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 7 reset
Device-Specific Information: f:\kkk\counter.rpt
counter
** EQUATIONS **
clock : INPUT;
Hold : INPUT;
reset : INPUT;
-- Node name is 'countNum0'
-- Equation name is 'countNum0', type is output
countNum0 = _LC1_A2;
-- Node name is 'countNum1'
-- Equation name is 'countNum1', type is output
countNum1 = _LC6_A2;
-- Node name is 'countNum2'
-- Equation name is 'countNum2', type is output
countNum2 = _LC3_A2;
-- Node name is 'countNum3'
-- Equation name is 'countNum3', type is output
countNum3 = _LC8_A4;
-- Node name is 'countNum4'
-- Equation name is 'countNum4', type is output
countNum4 = _LC6_A4;
-- Node name is 'countNum5'
-- Equation name is 'countNum5', type is output
countNum5 = _LC1_A4;
-- Node name is 'countNum6'
-- Equation name is 'countNum6', type is output
countNum6 = _LC2_A2;
-- Node name is '|LPM_ADD_SUB:160|addcore:adder|:121' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A2', type is buried
_LC5_A2 = LCELL( _EQ001);
_EQ001 = _LC1_A2 & _LC6_A2;
-- Node name is '|LPM_ADD_SUB:160|addcore:adder|:125' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A2', type is buried
!_LC4_A2 = _LC4_A2~NOT;
_LC4_A2~NOT = LCELL( _EQ002);
_EQ002 = !_LC3_A2
# !_LC6_A2
# !_LC1_A2;
-- Node name is '|LPM_ADD_SUB:160|addcore:adder|:129' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A4', type is buried
_LC3_A4 = LCELL( _EQ003);
_EQ003 = _LC4_A2 & _LC8_A4;
-- Node name is '|LPM_ADD_SUB:160|addcore:adder|:133' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A4', type is buried
_LC5_A4 = LCELL( _EQ004);
_EQ004 = _LC4_A2 & _LC6_A4 & _LC8_A4;
-- Node name is '|LPM_ADD_SUB:160|addcore:adder|:137' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A4', type is buried
_LC7_A4 = LCELL( _EQ005);
_EQ005 = _LC1_A4 & _LC4_A2 & _LC6_A4 & _LC8_A4;
-- Node name is ':4'
-- Equation name is '_LC2_A2', type is buried
_LC2_A2 = DFFE( _EQ006, GLOBAL( clock), GLOBAL(!reset), VCC, VCC);
_EQ006 = _LC2_A2 & _LC4_A4 & !_LC7_A4
# !_LC2_A2 & _LC4_A4 & _LC7_A4
# Hold & _LC2_A2;
-- Node name is ':6'
-- Equation name is '_LC1_A4', type is buried
_LC1_A4 = DFFE( _EQ007, GLOBAL( clock), GLOBAL(!reset), VCC, VCC);
_EQ007 = _LC1_A4 & _LC4_A4 & !_LC5_A4
# !_LC1_A4 & _LC4_A4 & _LC5_A4
# Hold & _LC1_A4;
-- Node name is ':8'
-- Equation name is '_LC6_A4', type is buried
_LC6_A4 = DFFE( _EQ008, GLOBAL( clock), GLOBAL(!reset), VCC, VCC);
_EQ008 = !_LC3_A4 & _LC4_A4 & _LC6_A4
# _LC3_A4 & _LC4_A4 & !_LC6_A4
# Hold & _LC6_A4;
-- Node name is ':10'
-- Equation name is '_LC8_A4', type is buried
_LC8_A4 = DFFE( _EQ009, GLOBAL( clock), GLOBAL(!reset), VCC, VCC);
_EQ009 = !_LC4_A2 & _LC4_A4 & _LC8_A4
# _LC4_A2 & _LC4_A4 & !_LC8_A4
# Hold & _LC8_A4;
-- Node name is ':12'
-- Equation name is '_LC3_A2', type is buried
_LC3_A2 = DFFE( _EQ010, GLOBAL( clock), GLOBAL(!reset), VCC, VCC);
_EQ010 = _LC3_A2 & _LC4_A4 & !_LC5_A2
# !_LC3_A2 & _LC4_A4 & _LC5_A2
# Hold & _LC3_A2;
-- Node name is ':14'
-- Equation name is '_LC6_A2', type is buried
_LC6_A2 = DFFE( _EQ011, GLOBAL( clock), GLOBAL(!reset), VCC, VCC);
_EQ011 = !_LC1_A2 & _LC4_A4 & _LC6_A2
# _LC1_A2 & _LC4_A4 & !_LC6_A2
# Hold & _LC6_A2;
-- Node name is ':16'
-- Equation name is '_LC1_A2', type is buried
_LC1_A2 = DFFE( _EQ012, GLOBAL( clock), GLOBAL(!reset), VCC, VCC);
_EQ012 = !Hold & !_LC1_A2
# Hold & _LC1_A2;
-- Node name is '~109~1'
-- Equation name is '~109~1', location is LC2_A4, type is buried.
-- synthesized logic cell
_LC2_A4 = LCELL( _EQ013);
_EQ013 = !_LC2_A2
# _LC1_A4
# _LC6_A4;
-- Node name is '~248~1'
-- Equation name is '~248~1', location is LC4_A4, type is buried.
-- synthesized logic cell
_LC4_A4 = LCELL( _EQ014);
_EQ014 = !Hold & !_LC8_A4
# !Hold & !_LC4_A2
# !Hold & _LC2_A4;
Project Information f:\kkk\counter.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 20,565K
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