fenwei2.rpt
来自「主次干道分别亮59s和11s」· RPT 代码 · 共 718 行 · 第 1/2 页
RPT
718 行
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\kkk\fenwei2.rpt
fenwei2
** EQUATIONS **
Numin0 : INPUT;
Numin1 : INPUT;
Numin2 : INPUT;
Numin3 : INPUT;
Numin4 : INPUT;
Numin5 : INPUT;
-- Node name is 'NumC0'
-- Equation name is 'NumC0', type is output
NumC0 = !_LC4_B7;
-- Node name is 'NumC1'
-- Equation name is 'NumC1', type is output
NumC1 = _LC5_B2;
-- Node name is 'NumC2'
-- Equation name is 'NumC2', type is output
NumC2 = _LC1_B2;
-- Node name is 'NumC3'
-- Equation name is 'NumC3', type is output
NumC3 = GND;
-- Node name is 'NumD0~1'
-- Equation name is 'NumD0~1', location is LC7_B13, type is buried.
-- synthesized logic cell
_LC7_B13 = LCELL( Numin0);
-- Node name is 'NumD0'
-- Equation name is 'NumD0', type is output
NumD0 = _LC7_B13;
-- Node name is 'NumD1'
-- Equation name is 'NumD1', type is output
NumD1 = _LC7_B2;
-- Node name is 'NumD2'
-- Equation name is 'NumD2', type is output
NumD2 = _LC1_B7;
-- Node name is 'NumD3'
-- Equation name is 'NumD3', type is output
NumD3 = _LC2_B3;
-- Node name is '|LPM_ADD_SUB:388|addcore:adder|:92' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC8_B7', type is buried
_LC8_B7 = LCELL( _EQ001);
_EQ001 = Numin1 & !Numin2
# !Numin1 & Numin2;
-- Node name is '|LPM_ADD_SUB:388|addcore:adder|:93' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC3_B3', type is buried
_LC3_B3 = LCELL( _EQ002);
_EQ002 = !_LC5_B9 & !Numin3
# _LC5_B9 & Numin3;
-- Node name is '|LPM_ADD_SUB:476|addcore:adder|:71' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B9', type is buried
_LC6_B9 = LCELL( _EQ003);
_EQ003 = Numin1 & Numin2;
-- Node name is '~119~1'
-- Equation name is '~119~1', location is LC2_B7, type is buried.
-- synthesized logic cell
_LC2_B7 = LCELL( _EQ004);
_EQ004 = !_LC1_B9 & _LC4_B2 & _LC4_B9;
-- Node name is ':119'
-- Equation name is '_LC3_B2', type is buried
_LC3_B2 = LCELL( _EQ005);
_EQ005 = !Numin5
# !Numin2
# !Numin3
# !Numin4;
-- Node name is ':153'
-- Equation name is '_LC3_B9', type is buried
!_LC3_B9 = _LC3_B9~NOT;
_LC3_B9~NOT = LCELL( _EQ006);
_EQ006 = !_LC5_B9 & Numin4 & Numin5
# Numin3 & Numin4 & Numin5;
-- Node name is ':187'
-- Equation name is '_LC2_B2', type is buried
_LC2_B2 = LCELL( _EQ007);
_EQ007 = !Numin3 & !Numin4
# !Numin5;
-- Node name is ':223'
-- Equation name is '_LC4_B9', type is buried
!_LC4_B9 = _LC4_B9~NOT;
_LC4_B9~NOT = LCELL( _EQ008);
_EQ008 = _LC6_B9 & Numin3 & Numin4
# Numin5;
-- Node name is ':260'
-- Equation name is '_LC4_B2', type is buried
_LC4_B2 = LCELL( _EQ009);
_EQ009 = !Numin2 & !Numin3
# !Numin4;
-- Node name is ':291'
-- Equation name is '_LC1_B9', type is buried
!_LC1_B9 = _LC1_B9~NOT;
_LC1_B9~NOT = LCELL( _EQ010);
_EQ010 = !_LC5_B9 & Numin3
# Numin4
# Numin5;
-- Node name is ':301'
-- Equation name is '_LC5_B9', type is buried
!_LC5_B9 = _LC5_B9~NOT;
_LC5_B9~NOT = LCELL( _EQ011);
_EQ011 = Numin1
# Numin2;
-- Node name is '~677~1'
-- Equation name is '~677~1', location is LC8_B2, type is buried.
-- synthesized logic cell
!_LC8_B2 = _LC8_B2~NOT;
_LC8_B2~NOT = LCELL( _EQ012);
_EQ012 = _LC2_B2 & _LC3_B9;
-- Node name is ':677'
-- Equation name is '_LC1_B2', type is buried
_LC1_B2 = LCELL( _EQ013);
_EQ013 = !_LC3_B9
# !_LC2_B2
# !_LC3_B2;
-- Node name is ':698'
-- Equation name is '_LC5_B2', type is buried
_LC5_B2 = LCELL( _EQ014);
_EQ014 = !_LC4_B2 & !_LC8_B2
# !_LC4_B9 & !_LC8_B2
# !_LC3_B2;
-- Node name is ':725'
-- Equation name is '_LC7_B9', type is buried
_LC7_B9 = LCELL( _EQ015);
_EQ015 = !_LC5_B9 & !Numin3 & Numin4
# !_LC5_B9 & !Numin3 & Numin5
# _LC5_B9 & Numin3;
-- Node name is ':728'
-- Equation name is '_LC8_B9', type is buried
_LC8_B9 = LCELL( _EQ016);
_EQ016 = _LC4_B2 & _LC7_B9
# !_LC4_B2 & Numin2 & Numin3
# !_LC4_B2 & !Numin2 & !Numin3;
-- Node name is ':731'
-- Equation name is '_LC2_B9', type is buried
_LC2_B9 = LCELL( _EQ017);
_EQ017 = _LC4_B9 & _LC8_B9
# !_LC4_B9 & _LC6_B9 & !Numin3
# !_LC4_B9 & !_LC6_B9 & Numin3;
-- Node name is ':734'
-- Equation name is '_LC1_B3', type is buried
_LC1_B3 = LCELL( _EQ018);
_EQ018 = _LC2_B2 & _LC2_B9
# !_LC2_B2 & !Numin3;
-- Node name is ':742'
-- Equation name is '_LC2_B3', type is buried
_LC2_B3 = LCELL( _EQ019);
_EQ019 = _LC1_B3 & _LC3_B2 & _LC3_B9
# _LC3_B2 & !_LC3_B3 & !_LC3_B9;
-- Node name is ':749'
-- Equation name is '_LC5_B7', type is buried
_LC5_B7 = LCELL( _EQ020);
_EQ020 = _LC1_B9 & _LC4_B2 & Numin2
# _LC4_B2 & Numin1 & Numin2
# !_LC1_B9 & !Numin1 & !Numin2
# !_LC4_B2 & !Numin2;
-- Node name is ':752'
-- Equation name is '_LC6_B7', type is buried
_LC6_B7 = LCELL( _EQ021);
_EQ021 = _LC4_B9 & _LC5_B7
# !_LC4_B9 & Numin1 & !Numin2
# !_LC4_B9 & !Numin1 & Numin2;
-- Node name is ':755'
-- Equation name is '_LC7_B7', type is buried
_LC7_B7 = LCELL( _EQ022);
_EQ022 = _LC2_B2 & _LC6_B7
# !_LC2_B2 & Numin2;
-- Node name is ':763'
-- Equation name is '_LC1_B7', type is buried
_LC1_B7 = LCELL( _EQ023);
_EQ023 = _LC3_B2 & _LC3_B9 & _LC7_B7
# _LC3_B2 & !_LC3_B9 & !_LC8_B7;
-- Node name is '~782~1'
-- Equation name is '~782~1', location is LC3_B7, type is buried.
-- synthesized logic cell
!_LC3_B7 = _LC3_B7~NOT;
_LC3_B7~NOT = LCELL( _EQ024);
_EQ024 = !_LC1_B9 & _LC4_B2
# !_LC4_B9;
-- Node name is '~782~2'
-- Equation name is '~782~2', location is LC4_B7, type is buried.
-- synthesized logic cell
!_LC4_B7 = _LC4_B7~NOT;
_LC4_B7~NOT = LCELL( _EQ025);
_EQ025 = _LC2_B2 & _LC3_B2 & !_LC3_B7
# _LC3_B2 & !_LC3_B9;
-- Node name is '~782~3'
-- Equation name is '~782~3', location is LC6_B2, type is buried.
-- synthesized logic cell
_LC6_B2 = LCELL( _EQ026);
_EQ026 = !_LC3_B9
# _LC2_B2 & _LC2_B7
# _LC2_B2 & Numin5;
-- Node name is ':782'
-- Equation name is '_LC7_B2', type is buried
_LC7_B2 = LCELL( _EQ027);
_EQ027 = _LC4_B7 & Numin1
# _LC3_B2 & _LC6_B2 & !Numin1;
Project Information f:\kkk\fenwei2.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 18,682K
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