fenwei2.vhd

来自「主次干道分别亮59s和11s」· VHDL 代码 · 共 36 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; 
ENTITY Fenwei2 IS
   PORT(Numin:IN integer RANGE 0 TO 63;
        NumC,NumD:OUT Integer RANGE 0 to 9);
END ENTITY;
ARCHITECTURE behavior OF Fenwei2 IS 
BEGIN
  process(Numin)
    BEGIN
     IF Numin>=60 THEN
		NumC<=6;
		NumD<=Numin-60;
	  ELSIF Numin>=50 THEN
		NumC<=5;
		NumD<=Numin-50;
	  ELSIF Numin>=40 THEN
		NumC<=4;
		NumD<=Numin-40;
	  ELSIF Numin>=30 THEN
		NumC<=3;
		NumD<=Numin-30;
	  ELSIF Numin>=20 THEN
		NumC<=2;
		NumD<=Numin-20;
	  ELSIF Numin>=10 THEN
		NumC<=1;
		NumD<=Numin-10;
	  ELSE 
		NumC<=0;
		NumD<=Numin;
	  END IF;
  END PROCESS;
END ARCHITECTURE behavior;