📄 jtd.rpt
字号:
- 2 - D 04 OR2 0 4 1 0 |FENWEI2:47|:698
- 3 - D 04 OR2 ! 0 3 0 1 |FENWEI2:47|:710
- 4 - D 04 OR2 ! 0 4 1 1 |FENWEI2:47|:721
- 3 - D 10 OR2 0 4 0 1 |FENWEI2:47|:725
- 4 - D 10 OR2 0 4 0 1 |FENWEI2:47|:728
- 5 - D 10 OR2 0 4 0 1 |FENWEI2:47|:731
- 6 - D 10 OR2 0 4 0 1 |FENWEI2:47|:734
- 7 - D 10 OR2 0 3 0 1 |FENWEI2:47|:738
- 1 - D 10 OR2 0 4 1 0 |FENWEI2:47|:742
- 3 - D 11 OR2 0 4 0 1 |FENWEI2:47|:749
- 1 - D 11 OR2 0 4 0 1 |FENWEI2:47|:752
- 4 - D 11 OR2 0 3 0 1 |FENWEI2:47|:755
- 8 - D 11 OR2 0 4 1 0 |FENWEI2:47|:763
- 1 - D 04 OR2 s 0 4 0 1 |FENWEI2:47|~782~1
- 5 - D 04 OR2 0 4 1 0 |FENWEI2:47|:782
- 2 - C 15 AND2 ! 0 2 0 4 |FENWEI:46|LPM_ADD_SUB:388|addcore:adder|pcarry2
- 5 - C 17 OR2 0 2 0 1 |FENWEI:46|LPM_ADD_SUB:388|addcore:adder|:92
- 2 - C 09 OR2 ! 0 2 0 2 |FENWEI:46|LPM_ADD_SUB:476|addcore:adder|:71
- 3 - C 03 AND2 s 0 3 0 1 |FENWEI:46|~119~1
- 1 - C 13 AND2 ! 0 4 0 6 |FENWEI:46|:119
- 2 - C 13 OR2 0 4 0 7 |FENWEI:46|:153
- 3 - C 13 OR2 ! 0 3 0 5 |FENWEI:46|:187
- 1 - C 09 OR2 0 4 0 5 |FENWEI:46|:223
- 2 - C 07 OR2 ! 0 3 0 4 |FENWEI:46|:260
- 3 - C 16 OR2 0 4 0 3 |FENWEI:46|:291
- 4 - C 03 AND2 s ! 0 2 0 1 |FENWEI:46|~677~1
- 7 - C 18 OR2 0 3 1 0 |FENWEI:46|:677
- 6 - C 03 OR2 0 4 1 0 |FENWEI:46|:698
- 7 - C 03 OR2 ! 0 3 0 1 |FENWEI:46|:710
- 5 - C 03 OR2 ! 0 4 1 1 |FENWEI:46|:721
- 8 - C 09 OR2 0 4 0 1 |FENWEI:46|:725
- 7 - C 09 OR2 0 4 0 1 |FENWEI:46|:728
- 6 - C 09 OR2 0 4 0 1 |FENWEI:46|:731
- 5 - C 09 OR2 0 4 0 1 |FENWEI:46|:734
- 3 - C 09 OR2 0 3 0 1 |FENWEI:46|:738
- 4 - C 09 OR2 0 4 1 0 |FENWEI:46|:742
- 1 - C 17 OR2 0 4 0 1 |FENWEI:46|:749
- 2 - C 17 OR2 0 4 0 1 |FENWEI:46|:752
- 4 - C 17 OR2 0 3 0 1 |FENWEI:46|:755
- 3 - C 17 OR2 0 4 1 0 |FENWEI:46|:763
- 2 - C 03 OR2 s 0 4 0 1 |FENWEI:46|~782~1
- 1 - C 03 OR2 0 4 1 0 |FENWEI:46|:782
- 6 - B 08 AND2 0 3 0 1 |FREDEVIDER:36|LPM_ADD_SUB:121|addcore:adder|:83
- 5 - B 08 AND2 0 4 0 3 |FREDEVIDER:36|LPM_ADD_SUB:121|addcore:adder|:87
- 2 - B 08 AND2 0 3 0 3 |FREDEVIDER:36|LPM_ADD_SUB:121|addcore:adder|:95
- 5 - B 15 AND2 0 2 0 1 |FREDEVIDER:36|LPM_ADD_SUB:121|addcore:adder|:99
- 4 - B 15 DFFE + 0 3 0 1 |FREDEVIDER:36|counter8 (|FREDEVIDER:36|:3)
- 3 - B 15 DFFE + 0 3 0 2 |FREDEVIDER:36|counter7 (|FREDEVIDER:36|:4)
- 2 - B 15 DFFE + 0 2 0 3 |FREDEVIDER:36|counter6 (|FREDEVIDER:36|:5)
- 4 - B 08 DFFE + 0 3 0 2 |FREDEVIDER:36|counter5 (|FREDEVIDER:36|:6)
- 8 - B 08 DFFE + 0 2 0 3 |FREDEVIDER:36|counter4 (|FREDEVIDER:36|:7)
- 7 - B 08 DFFE + 0 2 0 2 |FREDEVIDER:36|counter3 (|FREDEVIDER:36|:8)
- 1 - B 16 DFFE + 0 3 0 3 |FREDEVIDER:36|counter2 (|FREDEVIDER:36|:9)
- 1 - B 07 DFFE + 0 2 0 4 |FREDEVIDER:36|counter1 (|FREDEVIDER:36|:10)
- 1 - B 09 DFFE + 0 0 0 5 |FREDEVIDER:36|counter0 (|FREDEVIDER:36|:11)
- 1 - A 18 DFFE + 0 1 0 25 |FREDEVIDER:36|Clk (|FREDEVIDER:36|:12)
- 1 - B 15 OR2 s 0 3 0 1 |FREDEVIDER:36|~50~1
- 3 - B 08 OR2 s 0 4 0 1 |FREDEVIDER:36|~50~2
- 1 - B 08 OR2 ! 0 4 0 9 |FREDEVIDER:36|:50
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\eda\jhj\jtd.rpt
jtd
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/144( 2%) 19/ 72( 26%) 0/ 72( 0%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
B: 0/144( 0%) 6/ 72( 8%) 0/ 72( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/144( 0%) 18/ 72( 25%) 0/ 72( 0%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
D: 2/144( 1%) 16/ 72( 22%) 0/ 72( 0%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\eda\jhj\jtd.rpt
jtd
** CLOCK SIGNALS **
Type Fan-out Name
DFF 26 |FREDEVIDER:36|Clk
INPUT 10 CLK
Device-Specific Information: d:\eda\jhj\jtd.rpt
jtd
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 7 RESET
Device-Specific Information: d:\eda\jhj\jtd.rpt
jtd
** EQUATIONS **
CLK : INPUT;
HOLD : INPUT;
RESET : INPUT;
-- Node name is 'A0'
-- Equation name is 'A0', type is output
A0 = _LC5_C3;
-- Node name is 'A1'
-- Equation name is 'A1', type is output
A1 = _LC6_C3;
-- Node name is 'A2'
-- Equation name is 'A2', type is output
A2 = _LC7_C18;
-- Node name is 'A3'
-- Equation name is 'A3', type is output
A3 = GND;
-- Node name is 'B0'
-- Equation name is 'B0', type is output
B0 = _LC5_A7;
-- Node name is 'B1'
-- Equation name is 'B1', type is output
B1 = _LC1_C3;
-- Node name is 'B2'
-- Equation name is 'B2', type is output
B2 = _LC3_C17;
-- Node name is 'B3'
-- Equation name is 'B3', type is output
B3 = _LC4_C9;
-- Node name is 'C0'
-- Equation name is 'C0', type is output
C0 = _LC4_D4;
-- Node name is 'C1'
-- Equation name is 'C1', type is output
C1 = _LC2_D4;
-- Node name is 'C2'
-- Equation name is 'C2', type is output
C2 = _LC1_D12;
-- Node name is 'C3'
-- Equation name is 'C3', type is output
C3 = GND;
-- Node name is 'D0'
-- Equation name is 'D0', type is output
D0 = _LC1_A15;
-- Node name is 'D1'
-- Equation name is 'D1', type is output
D1 = _LC5_D4;
-- Node name is 'D2'
-- Equation name is 'D2', type is output
D2 = _LC8_D11;
-- Node name is 'D3'
-- Equation name is 'D3', type is output
D3 = _LC1_D10;
-- Node name is 'GREENA'
-- Equation name is 'GREENA', type is output
GREENA = _LC4_A2;
-- Node name is 'GREENB'
-- Equation name is 'GREENB', type is output
GREENB = _LC5_A14;
-- Node name is 'REDA'
-- Equation name is 'REDA', type is output
REDA = _LC1_A16;
-- Node name is 'REDB'
-- Equation name is 'REDB', type is output
REDB = _LC3_A13;
-- Node name is 'YELLOWA'
-- Equation name is 'YELLOWA', type is output
YELLOWA = _LC3_A2;
-- Node name is 'YELLOWB'
-- Equation name is 'YELLOWB', type is output
YELLOWB = _LC8_A5;
-- Node name is '|COUNTER:44|LPM_ADD_SUB:160|addcore:adder|:121' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A18', type is buried
!_LC2_A18 = _LC2_A18~NOT;
_LC2_A18~NOT = LCELL( _EQ001);
_EQ001 = !_LC1_A3
# !_LC4_A9;
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