counter.vhd

主次干道分别亮59s和11s

LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
ENTITY counter IS 
  PORT (clock:IN STD_LOGIC; 
        Hold:in std_logic; 
        reset:in std_logic;
        countNum:BuFFeR INTEGER RANGE 0 TO 79);
END ENTITY;
ARCHITECTURE behavior OF counter IS 
BEGIN
  process(reset,Clock)
    BEGIN
      IF Reset='1' THEN
         countNum<=0;
      ELSIF rising_edge(Clock) THEN
         IF Hold='1' then
            countNum<=countNum;
         ELSE
             IF countNum=79 THEN
                 countNum<=0;
             ELSE
                countNum<=countNum+1;
			 END IF;
		 END IF;
	  END IF;
  END process;
END ARCHITECTURE behavior;