syslib_5100.c

sysLib.c - generic PPC system-dependent library 5100BSP重要文件

/* sysLib.c - Motorola MVME5100 board series system-dependent library */

/* Copyright 1984-2002 Wind River Systems, Inc. */
/* Copyright 1996-2001 Motorola, Inc. All Rights Reserved */

/*
modification history
--------------------
01q,17jun02,kab  Clean up from review:
		 SPR 73642: sysBusTas* undefined symbols
01p,14mar02,kab  SPR 73218: ^X does not reboot
01o,30jan02,kab  Added MPC7410 (Nitro) support
01n,08nov01,kab  Changed CPU_TYPE_MAX (confusing codename) to CPU_TYPE_7400
                 Changed from Location Monitor label names to Unverise II
                 register access image naming (LM --> RAI) of labels.
		 Cleanup for T2.2
01m,15may01,pch  Move call of usrAltivecInit() from sysLib.c to usrConfig.c,
                 to fix an undefined reference when building bootrom.
01l,10may01,kab  Replaced calls to altivecInit(); altivecShowInit() with
		 usrAltivecInit()
01k,25apr01,srr  Change reference to global pciAutoConfigLib.
01l,16apr01,pcs  Moved altivecInit to sysHwInit2.
01k,02apr01,dtr  Porting altivec bsp changes from sp7400.
01j,09mar01,rhk  Additional Wind River coding standards changes.
01j,03nov00,rcs  fix path to pciAutoConfigLib.c
01i,16aug00,dmw  Wind River coding standards review.
01h,26may00,dmw  RTC Wathcdog support.
01g,12may00,dmw  Turned on board fail LED in sysToMonitor.
01f,08may00,dmw  Moved ROM point up by 4 in sysToMonitor for MAX errata.
01e,28apr00,srr  Removed debug definition of INCLUDE_SHOW_ROUTINES.
01d,19apr00,dmw  Added Max errata fix, vmxExcLoad.
01c,10apr00,dmw  Added mv2100 BSP's version of VME support.
01b,03apr00,dmw  Included "latest" ./pci/pciAutoConfigLib.h.
01a,10mar00,dmw  written. (from ver 01a of mv2400 bsp)
*/

/*
DESCRIPTION
This library provides board-specific routines.  The chip drivers included are:

    i8250Sio.c - Intel 8250 UART driver 
    ns8730xSuperIo.c	- Super I/O chip initialization
    ppcDecTimer.c - PowerPC decrementer timer library (system clock)
    byteNvRam.c - byte-oriented generic non-volatile RAM library
    pciConfigLib.c - PCI configuration library
    universe.c - Tundra Universe chip VME-to-PCI interface library
    HawkAuxClk.c - Hawk timer library (auxiliary clock)
    hawkMpic.c - Hawk Mpic / W83C553 PIB/IBC Interrupt Controller

SEE ALSO:
.pG "Configuration"
*/

/* includes */

#include "vxWorks.h"
#include "vme.h"
#include "memLib.h"
#include "cacheLib.h"
#include "sysLib.h"
#include "config.h"
#include "string.h"
#include "intLib.h"
#include "esf.h"
#include "excLib.h"
#include "logLib.h"
#include "taskLib.h"
#include "vxLib.h"
#include "tyLib.h"
#include "arch/ppc/archPpc.h"
#include "arch/ppc/mmu603Lib.h"
#include "arch/ppc/vxPpcLib.h"
#include "arch/ppc/excPpcLib.h"
#include "private/vmLibP.h"
#include "drv/pci/pciConfigLib.h"

#ifdef INCLUDE_ALTIVEC
#include "altivecLib.h"
IMPORT int       (* _func_altivecProbeRtn) () ;
#endif /* INCLUDE_ALTIVEC */

/* defines */

#define ZERO    0

#define DECREMENTER_PRESCALE    4
#define USECS_PER_SECOND        1000000

#define HAWK_PHB_ADDR( reg ) ( HAWK_PHB_BASE_ADRS + reg )

#ifdef INCLUDE_BPE
#   define HAWK_SMC_ADDR( reg ) ( HAWK_SMC_BASE_ADRS + reg )
#   define _PPC_HID0_DBP _PPC_HID0_ECPC
#endif /* INCLUDE_BPE */

/* globals */

/******************************************************************************
*
* NOMANUAL
*
* sysBatDesc[] is used to initialize the block address translation (BAT)
* registers within the PowerPC 603/604 MMU.  BAT hits take precedence
* over Page Table Entry (PTE) hits and are faster.  Overlap of memory
* coverage by BATs and PTEs is permitted in cases where either the IBATs
* or the DBATs do not provide the necessary mapping (PTEs apply to both
* instruction AND data space, without distinction).
*
* The primary means of memory control for VxWorks is the MMU PTE support
* provided by vmLib and cacheLib.  Use of BAT registers will conflict
* with vmLib support.  User's may use BAT registers for i/o mapping and
* other purposes but are cautioned that conflicts with cacheing and mapping
* through vmLib may arise.  Be aware that memory spaces mapped through a BAT
* are not mapped by a PTE and any vmLib() or cacheLib() operations on such
* areas will not be effective, nor will they report any error conditions.
*
* Note: BAT registers CANNOT be disabled - they are always active.
* For example, setting them all to zero will yield four identical data
* and instruction memory spaces starting at local address zero, each 128KB
* in size, and each set as write-back and cache-enabled.  Hence, the BAT regs
* MUST be configured carefully.
*
* With this in mind, it is recommended that the BAT registers be used
* to map LARGE memory areas external to the processor if possible.
* If not possible, map sections of high RAM and/or PROM space where
* fine grained control of memory access is not needed.  This has the
* beneficial effects of reducing PTE table size (8 bytes per 4k page)
* and increasing the speed of access to the largest possible memory space.
* Use the PTE table only for memory which needs fine grained (4KB pages)
* control or which is too small to be mapped by the BAT regs.
*
* The BAT configuration for 4xx/6xx-based PPC boards is as follows:
* All BATs point to PROM/FLASH memory so that end customer may configure
* them as required.
*
* [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
*/

UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT)] =
    {

    ((ROM_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | (_MMU_UBAT_BL_1M & /* I BAT 0 */
    ~(_MMU_UBAT_VS & _MMU_UBAT_VP))),
    ((ROM_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT),

    0, 0, /* I BAT 1 */

    0, 0, /* I BAT 2 */

    0, 0, /* I BAT 3 */

    0, 0, /* D BAT 0 */

    0, 0, /* D BAT 1 */

    0, 0, /* D BAT 2 */

    0, 0  /* D BAT 3 */
    };


/******************************************************************************
*
* NOMANUAL
*
* sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array
* used by the MMU to translate addresses with single page (4k) granularity.
* PTE memory space should not, in general, overlap BAT memory space but
* may be allowed if only Data or Instruction access is mapped via BAT.
*
* Address translations for local RAM, memory mapped PCI bus, memory mapped
* VME A16 space and local PROM/FLASH are set here.
*
* PTEs are held, strangely enough, in a Page Table.  Page Table sizes are
* integer powers of two based on amount of memory to be mapped and a
* minimum size of 64 kbytes.  The MINIMUM recommended Page Table sizes
* for 32-bit PowerPCs are:
*
* Total mapped memory        Page Table size
* -------------------        ---------------
*        8 Meg                 64 K
*       16 Meg                128 K
*       32 Meg                256 K
*       64 Meg                512 K
*      128 Meg                  1 Meg
*     .                .
*     .                .
*     .                .
*
* [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
*
* *** EXTENDED_VME configuration ***
*
* The user can use TLBs, and/or BATs, to map VME A32 space to the processor.
* The default is to use TLBs (MMU).  Change the table entry below to use
* a different method. (See "MODIFY A32 VME WINDOW HERE")
*/

PHYS_MEM_DESC sysPhysMemDesc [] =
    {

    /* Vector Table and Interrupt Stack */

    {
    (void *) LOCAL_MEM_LOCAL_ADRS,
    (void *) LOCAL_MEM_LOCAL_ADRS,
    RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE |
    VM_STATE_MEM_COHERENCY
    },

    /* Local DRAM - Must be second entry in sysPhysMemDesc for Auto Sizing */

    {
    (void *) RAM_LOW_ADRS,
    (void *) RAM_LOW_ADRS,
    LOCAL_MEM_SIZE -  RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE |
    VM_STATE_MEM_COHERENCY
    },

    /* Access to PCI ISA I/O space */

    {
    (void *) ISA_MSTR_IO_LOCAL,
    (void *) ISA_MSTR_IO_LOCAL,
    ISA_MSTR_IO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /* Access to PCI I/O space */

    {
    (void *) PCI_MSTR_IO_LOCAL,
    (void *) PCI_MSTR_IO_LOCAL,
    PCI_MSTR_IO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /*
     * Access to PCI memory space. Note: Guarding should not be required since
     * memory is well-behaved (no side-effects on read or write)
     */

    {
    (void *) PCI_MSTR_MEM_LOCAL,
    (void *) PCI_MSTR_MEM_LOCAL,
    PCI_MSTR_MEM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },

    /* Access to PCI memory I/O space */

    {
    (void *) PCI_MSTR_MEMIO_LOCAL,
    (void *) PCI_MSTR_MEMIO_LOCAL,
    PCI_MSTR_MEMIO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /* MODIFY A32 VME WINDOW HERE */

    {
    (void *) VME_A32_MSTR_LOCAL,
    (void *) VME_A32_MSTR_LOCAL,
    VME_A32_MSTR_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /* A24 VME WINDOW */

    {
    (void *) VME_A24_MSTR_LOCAL,
    (void *) VME_A24_MSTR_LOCAL,
    VME_A24_MSTR_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /* Off-board VME Universe Register Access Images */

    {
    (void *) VME_RAI_MSTR_LOCAL,
    (void *) VME_RAI_MSTR_LOCAL,
    VME_RAI_MSTR_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },

    /* A16 VME WINDOW */

    {
    (void *) VME_A16_MSTR_LOCAL,
    (void *) VME_A16_MSTR_LOCAL,
    VME_A16_MSTR_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /* MPIC Regs */

    {
    (void *) MPIC_BASE_ADRS,
    (void *) MPIC_BASE_ADRS,
    MPIC_REG_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /* HAWK SMC Registers */

    {
    (void *) HAWK_SMC_BASE_ADRS,
    (void *) HAWK_SMC_BASE_ADRS,
    HAWK_SMC_REG_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /* HAWK PHB Registers */

    {
    (void *) HAWK_PHB_BASE_ADRS,
    (void *) HAWK_PHB_BASE_ADRS,
    HAWK_PHB_REG_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    {
    (void *) FLASH_BASE_ADRS,
    (void *) FLASH_BASE_ADRS,
    FLASH_MEM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    }
    };

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);

int    sysBus      = VME_BUS;         /* system bus type */
int    sysCpu      = CPU;             /* system CPU type (MC680x0) */
char * sysBootLine = BOOT_LINE_ADRS;  /* address of boot line */
char * sysExcMsg   = EXC_MSG_ADRS;    /* catastrophic message area */
int    sysProcNum;                    /* processor number of this CPU */
int    sysFlags;                      /* boot flags */
char   sysBootHost [BOOT_FIELD_LEN];  /* name of host from which we booted */
char   sysBootFile [BOOT_FIELD_LEN];  /* name of file from which we booted */
UINT   sysVectorIRQ0  = INT_VEC_IRQ0; /* vector for IRQ0 */
BOOL   sysVmeEnable   = FALSE;        /* by default no VME */
static int   sysHawkPciBusNo;         /* Hawk Config Space BDF address */
static int   sysHawkPciDevNo;
static int   sysHawkPciFuncNo;

unsigned char clearWd [1]  = { 0x00 };

/* locals */

LOCAL char sysModelStr[80];
LOCAL char wrongCpuMsg[] = WRONG_CPU_MSG; 

/* forward declarations */

void    sysSpuriousIntHandler (void);
void    sysCpuCheck (void);
char *  sysPhysMemTop (void);
STATUS  sysPciExtHawkInit (int, int, int);
UCHAR   sysNvRead (ULONG);
void    sysNvWrite (ULONG, UCHAR);
void    sysBusTasClear (volatile char *);
STATUS  sysBusProbe (char *, int, int, char *);
IMPORT UINT sysHid1Get (void);

#ifdef ANY_BRDS_IN_CHASSIS_NOT_RMW
LOCAL BOOL sysVmeVownTas (char *);
#endif /* ANY_BRDS_IN_CHASSIS_NOT_RMW */

LOCAL   BOOL sysVmeRmwTas (char *);
void    sysConfigBpe (void);
void    reportBootromErrors (void);

/* externals */

IMPORT UCHAR  sysInByte (ULONG);
IMPORT void   sysOutByte (ULONG, UCHAR);
IMPORT UINT16 sysIn16 (UINT16 *);
IMPORT void   sysOut16 (UINT16 *, UINT16);
IMPORT UINT32 sysIn32 (UINT32 *);
IMPORT void   sysOut32 (UINT32 *, UINT32);
IMPORT void   sysPciRead32 (UINT32, UINT32 *);
IMPORT void   sysPciWrite32 (UINT32, UINT32);
IMPORT void   sysClkIntCIO (void);
IMPORT STATUS sysMemProbeSup (int length, char * src, char * dest);
IMPORT int    sysProbeExc();
IMPORT VOIDFUNCPTR      smUtilTasClearRtn;
IMPORT void   sysBusRmwEnable(UINT, UINT, UINT, char *);
IMPORT void   sysBusRmwDisable(void);
IMPORT UINT32 sysTimeBaseLGet (void);
IMPORT UCHAR  sysProductStr[];

/* BSP DRIVERS */

#if defined (INCLUDE_PCI)
#    include "pci/pciConfigLib.c"       /* PCI config space access */
#    include "pci/pciIntLib.c"          /* PCI int support */
#    ifdef INCLUDE_SHOW_ROUTINES
#       include "pci/pciConfigShow.c"   /* PCI config space display */
#    endif /* INCLUDE_SHOW_ROUTINES */
#    ifdef INCLUDE_PCI_AUTOCONF         /* Yellowknife uses autoconfig */
#       include "pci/pciAutoConfigLib.c"/* automatic PCI configuration */
#       include "sysBusPci.c"           /* pciAutoConfig BSP support file */
#    endif /*  INCLUDE_PCI_AUTOCONF */
#endif /* INCLUDE_PCI */

#ifdef INCLUDE_NETWORK
#   include "./sysNet.c"
#   ifdef INCLUDE_END
#       ifdef INCLUDE_MCG_END
#      include "./sysEnd.c"