syslib_765.c

sysLib.c - generic PPC system-dependent library 765BSP重要文件

/* sysLib.c - Motorola MCPN765 board series system-dependent library */

/* Copyright 1984-2000 Wind River Systems, Inc. */
/* Copyright 1996-2000 Motorola, Inc. All Rights Reserved */

/*
modification history
--------------------
01q,21jun02,mil  Updated sysSmAnchorFind().
01p,23may02,mil  Updated shared memory macros and sysSmAnchorFind() (SPR
                 #76002).
01o,28mar02,mil  Updated for MPC7410 (Nitro) revision 1.4.
01n,13mar02,kab  Remove vmxExcLoad - SPR 74268
01m,04feb02,mil  Renamed sysEnd.c to sysDec21x40End.c, moved various END
                 routines into the new sysDec21x40End.c.
01l,07nov01,mil  Cleaned up compiler warnings.
01k,11oct01,mil  Merged from post T2.1 release into T2.2.
01j,21aug01,mil  Added secondary ethernet support.
01i,01aug01,mil  Added support for Altivec.
01h,06sep00,srr  Add new networking driver support.
01g,27jun00,dmw  Inclusion of pci/pciAutoConfig.c changed to 
                 drv/pci/pciAutoConfigLib.h per WRS code review.
01f,29oct99,srr  Removed INCLUDE_ATA around sysHwInit variables.
01e,27oct99,dmw  Added function sysDramSize().
01d,13oct99,rhk  added ATA driver support.
01c,19oct99,srr  Added PIB/IBC support.
01b,12oct99,srr  Added Max support: disabling L2 cache in sysHwInit,
                 update sysModel, add offset to warm reboot, and add vmxExcLoad.
01a,27sep99,dmw  Written (from version 01c of ppmc750/sysLib.c).
*/

/*
DESCRIPTION
This library provides board-specific routines.  The chip drivers included are:

    i8250Sio.c 		- Intel 8250 UART driver 
    ppcDecTimer.c 	- PowerPC decrementer timer library (system clock)
    byteNvRam.c 	- byte-oriented generic non-volatile RAM library
    pciConfigLib.c 	- PCI configuration library
    dec2155xCpci.c 	- Dec/Intel non-transparent PCI-to-PCI bridge library
    HawkAuxClk.c 	- Hawk timer library (auxiliary clock)
    ataDrv.o            - ATA/EIDE interface driver

    sl82565IntrCtl.c    - interrupt controller driver
         or
    hawkMpic.c          - Hawk Mpic / W83C553 PIB/IBC Interrupt Controller

INCLUDE FILES: sysLib.h

SEE ALSO:
.pG "Configuration"
*/

/* includes */

#include "vxWorks.h"
#include "pci.h"
#include "memLib.h"
#include "cacheLib.h"
#include "sysLib.h"
#include "config.h"
#include "string.h"
#include "intLib.h"
#include "esf.h"
#include "excLib.h"
#include "logLib.h"
#include "taskLib.h"
#include "vxLib.h"
#include "tyLib.h"
#include "arch/ppc/archPpc.h"
#include "arch/ppc/mmu603Lib.h"
#include "arch/ppc/vxPpcLib.h"
#include "arch/ppc/excPpcLib.h"
#include "private/vmLibP.h"
#include "drv/pci/pciConfigLib.h"
#ifdef INCLUDE_DEC2155X
#   include "dec2155xCpci.h"
#endif
#ifdef INCLUDE_SM_COMMON
#   include "smLib.h"
#   include "smUtilLib.h"
#   include "smPktLib.h"
#   include "smObjLib.h"
#endif  /* INCLUDE_SM_COMMON */
#ifdef INCLUDE_ALTIVEC
#   include "altivecLib.h"
    IMPORT int (* _func_altivecProbeRtn) () ;
#endif /* INCLUDE_ALTIVEC */


/* defines */

#define ZERO	0

#define DEFAULT_TAS_CHECKS	10		/* rechecks for soft tas */
#define TAS_CONST		0x80

#define HAWK_PHB_ADDR( reg ) ( HAWK_PHB_BASE_ADRS + reg )

#ifdef INCLUDE_BPE

#   define HAWK_SMC_ADDR( reg ) ( HAWK_SMC_BASE_ADRS + reg )

#   define _PPC_HID0_DBP _PPC_HID0_ECPC

#endif /* INCLUDE_BPE */

#ifdef INCLUDE_DPM	/* dynamic power management */

#   define HAWK_SMC_ADDR( reg ) ( HAWK_SMC_BASE_ADRS + reg )

#   define _PPC_HID0_BIT_DPM	11 /* dynamic power management bit */
#   define _PPC_HID0_DPM        (1<<(31-_PPC_HID0_BIT_DPM))

#endif /* INCLUDE_DPM */

#define DEFAULT_HAWK_PCI_BUS_NUMBER	0
#define DEFAULT_HAWK_PCI_DEV_NUMBER	0
#define DEFAULT_HAWK_PCI_FUNC_NUMBER	0

#define HAWK_ADDR( reg )	( HAWK_PHB_BASE_ADRS + reg )
#define HAWK_RDWR_ENA		(CPU2PCI_ATTR_REN | CPU2PCI_ATTR_WEN)

#define HAWK_ERR_STS_MSK (HAWK_MPC_MEREN_RTAI | \
		          HAWK_MPC_MEREN_SMAI | \
			  HAWK_MPC_MEREN_SERRI)

#define HAWK_ERR_DIS (HAWK_MPC_MEREN_RTAI  | \
		      HAWK_MPC_MEREN_SMAI  | \
		      HAWK_MPC_MEREN_SERRI | \
		      HAWK_MPC_MEREN_RTAM  | \
		      HAWK_MPC_MEREN_SMAM  | \
		      HAWK_MPC_MEREN_SERRM)

#define SYS_DECS_DRAM_INDEX	1
#define SYS_DECS_PCI_IO_INDEX	2
#define SYS_DECS_PCI_MEM_INDEX	3

/* structures */

typedef struct hawkWinStruct
    {
    UINT32 winType;   /* mem or i/o */
    UINT32 winBase;   /* start of window */
    UINT32 winLimit;  /* end of window */
    } HAWK_WIN_STRUCT;

typedef struct hawkOffsets
    {
    UINT32 range;
    UINT32 offset;
    UINT32 attr;
    } HAWK_OFFSETS;

HAWK_OFFSETS	sysHawkCpuWinOff [] =
    {

	{
	HAWK_ADDR(HAWK_MPC_MSADD0),
	HAWK_ADDR(HAWK_MPC_MSOFF0),
	HAWK_ADDR(HAWK_MPC_MSATT0)
	},

	{
	HAWK_ADDR(HAWK_MPC_MSADD1),
	HAWK_ADDR(HAWK_MPC_MSOFF1),
	HAWK_ADDR(HAWK_MPC_MSATT1)
	},

	{
	HAWK_ADDR(HAWK_MPC_MSADD2),
	HAWK_ADDR(HAWK_MPC_MSOFF2),
	HAWK_ADDR(HAWK_MPC_MSATT2)
	},

	{
	HAWK_ADDR(HAWK_MPC_MSADD3),
	HAWK_ADDR(HAWK_MPC_MSOFF3),
	HAWK_ADDR(HAWK_MPC_MSATT3)
	}

    };

HAWK_OFFSETS	sysHawkPciWinOff [] =
    {

    {PCI_CFG_HAWK_PSADD0, PCI_CFG_HAWK_PSOFF0, PCI_CFG_HAWK_PSATT0},
    {PCI_CFG_HAWK_PSADD1, PCI_CFG_HAWK_PSOFF1, PCI_CFG_HAWK_PSATT1},
    {PCI_CFG_HAWK_PSADD2, PCI_CFG_HAWK_PSOFF2, PCI_CFG_HAWK_PSATT2},
    {PCI_CFG_HAWK_PSADD3, PCI_CFG_HAWK_PSOFF3, PCI_CFG_HAWK_PSATT3}

    };

#define HAWK_CPU_WIN_CNT (sizeof (sysHawkCpuWinOff)/ sizeof (HAWK_OFFSETS))
#define HAWK_PCI_WIN_CNT (sizeof (sysHawkPciWinOff)/ sizeof (HAWK_OFFSETS))
#define HAWK_WIN_CNT (HAWK_CPU_WIN_CNT + HAWK_PCI_WIN_CNT)

/* globals */

static char * sysPhysMemSize = NULL;	/* ptr to top of mem + 1 */

/*
 * sysBatDesc[] is used to initialize the block address translation (BAT)
 * registers within the PowerPC 603/604 MMU.  BAT hits take precedence
 * over Page Table Entry (PTE) hits and are faster.  Overlap of memory
 * coverage by BATs and PTEs is permitted in cases where either the IBATs
 * or the DBATs do not provide the necessary mapping (PTEs apply to both
 * instruction AND data space, without distinction).
 *
 * The primary means of memory control for VxWorks is the MMU PTE support
 * provided by vmLib and cacheLib.  Use of BAT registers will conflict
 * with vmLib support.  User's may use BAT registers for i/o mapping and
 * other purposes but are cautioned that conflicts with cacheing and mapping
 * through vmLib may arise.  Be aware that memory spaces mapped through a BAT
 * are not mapped by a PTE and any vmLib() or cacheLib() operations on such
 * areas will not be effective, nor will they report any error conditions.
 *
 * Note: BAT registers can be disabled if the VS and VP bits are both clear
 * in the upper BAT register of each pair.  In the default configuration
 * (coded below) the VS and VP bits are cleared and thus the BAT registers
 * are disabled.  To enable the BAT registers, change the construct coded
 * below the upper BAT register:
 *
 *.CS
 *	      & ~(_MMU_UBAT_VS | _MMU_UBAT_VP)),
 *	      which clears VS and VP
 *				to
 *	      | (_MMU_UBAT_VS | _MMU_UBAT_VP)),
 *	      which sets VS and VP
 *.CE
 *
 * With this in mind, it is recommended that the BAT registers be used
 * to map LARGE memory areas external to the processor if possible.
 * If not possible, map sections of high RAM and/or PROM space where
 * fine grained control of memory access is not needed.  This has the
 * beneficial effects of reducing PTE table size (8 bytes per 4k page)
 * and increasing the speed of access to the largest possible memory space.
 * Use the PTE table only for memory which needs fine grained (4KB pages)
 * control or which is too small to be mapped by the BAT regs.
 *
 * The BAT configuration for 4xx/6xx-based PPC boards is as follows:
 * All BATs point to PROM/FLASH memory so that end customer may configure
 * them as required.
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 */

UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT)] =
    {
    /* I BAT 0 */

    ((ROM_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | (_MMU_UBAT_BL_1M &
    ~(_MMU_UBAT_VS & _MMU_UBAT_VP))),
    ((ROM_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT),

    /* I BAT 1 */

    0, 0,

    /* I BAT 2 */

    0, 0,

    /* I BAT 3 */

    0, 0,

    /* D BAT 0 */

    0, 0,

    /* D BAT 1 */

    0, 0,

    /* D BAT 2 */

    0, 0,

    /* D BAT 3 */

    0, 0
    };

/*
 * sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array
 * used by the MMU to translate addresses with single page (4k) granularity.
 * PTE memory space should not, in general, overlap BAT memory space but
 * may be allowed if only Data or Instruction access is mapped via BAT.
 *
 * Address translations for local RAM, memory mapped PCI bus and local
 * PROM/FLASH are set here.
 *
 * PTEs are held, strangely enough, in a Page Table.  Page Table sizes are
 * integer powers of two based on amount of memory to be mapped and a
 * minimum size of 64 kbytes.  The MINIMUM recommended Page Table sizes
 * for 32-bit PowerPCs are:
 *
 *.CS
 * Total mapped memory		Page Table size
 * -------------------		---------------
 *        8 Meg			     64 K
 *       16 Meg			    128 K
 *       32 Meg			    256 K
 *       64 Meg			    512 K
 *      128 Meg			      1 Meg
 * 	.				.
 * 	.				.
 * 	.				.
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 *.CE
 *
 */

PHYS_MEM_DESC sysPhysMemDesc [] =
    {
    {
    /* Vector Table and Interrupt Stack */

    (void *) LOCAL_MEM_LOCAL_ADRS,
    (void *) LOCAL_MEM_LOCAL_ADRS,
    RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE |
    VM_STATE_MEM_COHERENCY
    },

    {
    /* 
     * Local DRAM - Must be SYS_DECS_DRAM_INDEX entry in sysPhysMemDesc for 
     * Auto Sizing 
     */

    (void *) RAM_LOW_ADRS,
    (void *) RAM_LOW_ADRS,
    LOCAL_MEM_SIZE -  RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE |
    VM_STATE_MEM_COHERENCY
    },

    /* 
     * Access to PCI ISA memory space - Must be SYS_DECS_PCI_IO_INDEX entry in 
     * sysPhysMemDesc for Extended PCI configuration.
     */

    {
#ifdef EXTENDED_PCI
    (void *) 0,	/* Calculated at run-time */
    (void *) 0,	/* Calculated at run-time */
#else
    (void *) PCI_MSTR_MEMIO_LOCAL,
    (void *) PCI_MSTR_MEMIO_LOCAL,
#endif /* EXTENDED_PCI */
    PCI_MSTR_MEMIO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /*
     * Access to PCI memory space - Must be SYS_DECS_PCI_MEM_INDEX entry in 
     * sysPhysMemDesc for Extended PCI configuration. 
     * Note: Guarding should not be required since
     * memory is well-behaved (no side-effects on read or write)
     */

    {
#ifdef EXTENDED_PCI
    (void *) 0,	/* Calculated at run-time */
    (void *) 0,	/* Calculated at run-time */
#else
    (void *) PCI_MSTR_MEM_LOCAL,
    (void *) PCI_MSTR_MEM_LOCAL,
#endif /* EXTENDED_PCI */
    PCI_MSTR_MEM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },

    /* Access to PCI ISA I/O space */

    {
    (void *) ISA_MSTR_IO_LOCAL,
    (void *) ISA_MSTR_IO_LOCAL,
    ISA_MSTR_IO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /* Access to PCI I/O space */

    {
    (void *) PCI_MSTR_IO_LOCAL,
    (void *) PCI_MSTR_IO_LOCAL,
    PCI_MSTR_IO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    {
    /* MPIC Regs */

    (void *) MPIC_BASE_ADRS,
    (void *) MPIC_BASE_ADRS,
    MPIC_REG_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    {
    (void *) HAWK_SMC_BASE_ADRS,
    (void *) HAWK_SMC_BASE_ADRS,
    HAWK_SMC_REG_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    {
    (void *) HAWK_PHB_BASE_ADRS,
    (void *) HAWK_PHB_BASE_ADRS,
    HAWK_PHB_REG_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    {
    (void *) FLASH_BASE_ADRS,
    (void *) FLASH_BASE_ADRS,
    FLASH_MEM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    }
    };

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);

int   sysBus	   = BUS_TYPE_PCI;	/* system bus type */
int   sysCpu	   = CPU;		/* CPU type */
char * sysBootLine = BOOT_LINE_ADRS;	/* address of boot line */
char * sysExcMsg   = EXC_MSG_ADRS;	/* catastrophic message area */
int    sysProcNum;			/* processor number of this CPU */
int    sysFlags;			/* boot flags */
char   sysBootHost [BOOT_FIELD_LEN];	/* name of host from which we booted */
char   sysBootFile [BOOT_FIELD_LEN];	/* name of file from which we booted */
UINT   sysVectorIRQ0  = INT_VEC_IRQ0;	/* vector for IRQ0 */
static int   sysHawkPciBusNo;           /* Hawk Config Space BDF address */
static int   sysHawkPciDevNo;
static int   sysHawkPciFuncNo;

int    smIntArg1 = -1;			/* Shared memory SM_INT_ARG1 */
int    smIntArg2 = -1;			/* Shared memory SM_INT_ARG2 */

HAWK_WIN_STRUCT sysHawkCpuToPciWin[HAWK_WIN_CNT] = { { 0 } };
HAWK_WIN_STRUCT sysHawkPciToCpuWin[HAWK_WIN_CNT] = { { 0 } };
int   sysValidHawkWindows = 0;		/* number of valid entries */