syslib7445.c

sysLib.c - generic PPC system-dependent library 7445BSP重要文件

        *(short *)ioAddr = *bufPtr++;
    PPC_EIEIO_SYNC;
    }

/*******************************************************************************
*
* sysInLongString - reads a string of longwords from an io address.
*
* This function reads a longword string from a specified io address.
*
* RETURNS: N/A
*/

void sysInLongString
    (
    ULONG    ioAddr,
    ULONG *  bufPtr,
    int      nLongs
    )
    {
    int loopCtr;

    for (loopCtr = 0; loopCtr < nLongs; loopCtr++)
        *bufPtr++ = *(int *)ioAddr;
    PPC_EIEIO_SYNC;
    }

/*******************************************************************************
*
* sysOutLongString - writes a string of longwords to an io address.
*
* This function writes a longword string from a specified io address.
*
* RETURNS: N/A
*/

void sysOutLongString
    (
    ULONG	ioAddr,
    ULONG *	bufPtr,
    int		nLongs 
    )
    {
    int loopCtr;

    for (loopCtr = 0; loopCtr < nLongs; loopCtr++)
        *(int *)ioAddr = *bufPtr++;
    PPC_EIEIO_SYNC;
    }
#endif	/* INCLUDE_ATA */



/*******************************************************************************
*
* sys107RegRead - read a 32-bit address MPC107 register
*
* Read a 32-bit address MPC107 register and returns
* a 32 bit value.  Swap the address to little endian before  
* writing it to config address since it is PCI, and swap the 
* value to big endian before returning to the caller.
*
* RETURNS: The contents of the specified MPC107 register.
*/

ULONG sys107RegRead
    ( 
    ULONG regNum 
    )
    {
    ULONG temp;

    /* swap the value to little endian */

    *(ULONG *) sysPciConfAddr = LONGSWAP(regNum); 

    PPC_EIEIO_SYNC;

    temp = *(ULONG *) sysPciConfData;

    PPC_EIEIO_SYNC;

    /* swap the data & return */

    return (LONGSWAP (temp));		
    }

/*******************************************************************************
*
* sys107RegWrite - write a 32-bit MPC107 register
*
* write a 32-bit address MPC107 register.
* Swap the address to little endian before writing it to config 
* address, and swap the value to little endian before writing.
*
* RETURNS: N/A
*/

void sys107RegWrite
    ( 
    ULONG regNum,
    ULONG value
    )
    {
    ULONG temp;

    /* swap the value to little endian */

    *(ULONG *) sysPciConfAddr = LONGSWAP(regNum); 

    PPC_EIEIO_SYNC;

    temp = LONGSWAP (value);

    *(ULONG *) sysPciConfData = temp;

    PPC_EIEIO_SYNC;

    }


/*******************************************************************************
*
* sysMemMapDetect - detect PCI address map A or B
* 
* This procedure detects the address map (A or B) on the Sandpoint and
* assigns proper values to some global variables.  First it assumes
* that the memory map is of Map B, then reads the Vendor and Device
* ids.  If the value does not match with what is expected, all global
* variables are then set for Map A.
*
* The following global variables are set to reflect the PCI address map:
* .CS
*    sysPciConfAddr
*    sysPciConfData 	
*    sysPciMstrCfgAdrs	
*    sysPciMstrIoLocal
*    sysPciMstrIackLocal	
*    sysPciMstrIsaMemLocal
*    sysPciMstrMemIoLocal
*    sysPciSlvMemLocal	
*    sysPciMstrMemIoBus	
* .CE
*
* RETURNS: N/A
*/

void sysMemMapDetect
    (
    void
    )
    {
    ULONG retVal;

    sysPciConfAddr              = MPC107_CFG_ADDR_CHRP;
    sysPciConfData              = MPC107_CFG_DATA_CHRP;
    sysPciMstrIsaIoLocal	= PCI_MSTR_ISA_IO_LOCAL_B;
    sysPciMstrCfgAdrs		= PCI_MSTR_CNFG_ADRS_B;
    sysPciMstrIoLocal		= PCI_MSTR_IO_LOCAL_B;
    sysPciMstrIackLocal		= PCI_MSTR_IACK_LOCAL_B;
    sysPciMstrIsaMemLocal	= PCI_MSTR_ISA_MEM_LOCAL_B;
    sysPciMstrMemIoLocal	= PCI_MSTR_MEMIO_LOCAL_B;
    sysPciSlvMemLocal		= PCI_SLV_MEM_LOCAL_B;
    sysPciMstrMemIoBus		= PCI_MSTR_MEMIO_BUS_B;

    retVal = sys107RegRead(MPC107_CFG_BASE);	/* Read Device & Vendor Ids */

    if ((retVal == MPC107_DEV_VEN_ID) ||	/* cmp with expected value */
        (retVal == PPMC8245_ID)     ||
        (retVal == MPC107_DEV_ID))
        {
        return;
        }
    else
        {
	sysPciConfAddr 		= MPC107_CFG_ADDR_PREP;
	sysPciConfData 		= MPC107_CFG_DATA_PREP;
	sysPciMstrIsaIoLocal	= PCI_MSTR_ISA_IO_LOCAL_A;
	sysPciMstrCfgAdrs	= PCI_MSTR_CNFG_ADRS_A;
        sysPciMstrIoLocal	= PCI_MSTR_IO_LOCAL_A;
	sysPciMstrIackLocal	= PCI_MSTR_IACK_LOCAL_A;
	sysPciMstrIsaMemLocal	= PCI_MSTR_ISA_MEM_LOCAL_A;
	sysPciMstrMemIoLocal	= PCI_MSTR_MEMIO_LOCAL_A;
        sysPciSlvMemLocal	= PCI_SLV_MEM_LOCAL_A;
	sysPciMstrMemIoBus	= PCI_MSTR_MEMIO_BUS_A;
        }

    PPC_EIEIO_SYNC;  
    }

/*******************************************************************************
*
* sysEUMBBARRead - read a register from the EPIC address space
*
* This function reads a register from the EPIC address space. The
* register number <regNum> is added to the offset of the EPIC base address
*
* NOMANUAL
*
* RETURNS:  the 32 bit little endian value of the register.
*/

ULONG sysEUMBBARRead
    (
    ULONG regNum
    )
    {
    ULONG temp;

    PPC_EIEIO_SYNC;  
    temp = *(ULONG *) (EUMBBAR_VAL + regNum) ;
    return (LONGSWAP(temp));
    }
	
/*******************************************************************************
*
* sysEUMBBARWrite -  write a register to the EPIC address space
*
* This function wrties a register to the EPIC address space. The
* register number <regNum> is added to the offset of the EPIC base address
* and the resulting address is loaded with <regVal>
*
* NOMANUAL
*
* RETURNS: N/A
*/

void sysEUMBBARWrite
    (
    ULONG regNum,
    ULONG regVal
    )
    {
  
    *(ULONG *) (EUMBBAR_VAL + regNum) = LONGSWAP(regVal);
    PPC_EIEIO_SYNC;  
    return ;
    }

#if  defined(INCLUDE_NVRAM)
/*******************************************************************************
*
* sysNvramHwInit - initialize the NVRAM to use for boot string
*
* This routine initializes the NVRAM on the Sandpoint BBSRAM.
*
* RETURNS: N/A
*/

void sysNvramHwInit 
    (
    void
    )
    {
    /* Enable the RTC and PWR registers */

    sysSioWrite (SUPER_IO_BASE_ADRS, SIO_LUNINDEX, SIO_LUN_RTC);
    sysSioWrite (SUPER_IO_BASE_ADRS, SIO_ACTIVATE, SIO_LUNDISABLE);
    sysSioWrite (SUPER_IO_BASE_ADRS, SIO_IOBASEHI, SUPER_IO_RTC_BASEHI);
    sysSioWrite (SUPER_IO_BASE_ADRS, SIO_IOBASELO, SUPER_IO_RTC_BASELO);
    sysSioWrite (SUPER_IO_BASE_ADRS, SIO_ACTIVATE, SIO_LUNENABLE);
    sysSioWrite (SUPER_IO_BASE_ADRS, SIO_LUNINDEX, SIO_LUN_PWR);
    sysSioWrite (SUPER_IO_BASE_ADRS, SIO_ACTIVATE, SIO_LUNENABLE);

    /* Init the card control/Chip select registers */

    /* CS0 Base Address MSB Register */

    sysSioWrite (SUPER_IO_BASE_ADRS, SIO_PCSCI, SIO_CS0_MSB);
    sysSioWrite (SUPER_IO_BASE_ADRS, SIO_PCSCD, MSB(DATA_REG));

    /* CS0 Base Address LSB Register */

    sysSioWrite (SUPER_IO_BASE_ADRS, SIO_PCSCI, SIO_CS0_LSB);
    sysSioWrite (SUPER_IO_BASE_ADRS, SIO_PCSCD, LSB(DATA_REG));

    /* CS0 Configuration Register */

    sysSioWrite (SUPER_IO_BASE_ADRS, SIO_PCSCI, SIO_CS0_CFG);
    sysSioWrite (SUPER_IO_BASE_ADRS, SIO_PCSCD, NV_RAM_CSX_CNFG);

    /* CS1 Base Address MSB Register */

    sysSioWrite (SUPER_IO_BASE_ADRS, SIO_PCSCI, SIO_CS1_MSB);
    sysSioWrite (SUPER_IO_BASE_ADRS, SIO_PCSCD, MSB(LSB_INDX_REG));

    /* CS1 Base Address LSB Register */

    sysSioWrite (SUPER_IO_BASE_ADRS, SIO_PCSCI, SIO_CS1_LSB);
    sysSioWrite (SUPER_IO_BASE_ADRS, SIO_PCSCD, LSB(LSB_INDX_REG));

    /* CS1 Configuration Register */

    sysSioWrite (SUPER_IO_BASE_ADRS, SIO_PCSCI, SIO_CS1_CFG);
    sysSioWrite (SUPER_IO_BASE_ADRS, SIO_PCSCD, NV_RAM_CSX_CNFG);

    /* CS2 Base Address MSB Register */

    sysSioWrite (SUPER_IO_BASE_ADRS, SIO_PCSCI, SIO_CS2_MSB);
    sysSioWrite (SUPER_IO_BASE_ADRS, SIO_PCSCD, MSB(MSB_INDX_REG));

    /* CS2 Base Address LSB Register */

    sysSioWrite (SUPER_IO_BASE_ADRS, SIO_PCSCI, SIO_CS2_LSB);
    sysSioWrite (SUPER_IO_BASE_ADRS, SIO_PCSCD, LSB(MSB_INDX_REG)); 

    /* CS2 Configuration Register */   

    sysSioWrite (SUPER_IO_BASE_ADRS, SIO_PCSCI, SIO_CS2_CFG);
    sysSioWrite (SUPER_IO_BASE_ADRS, SIO_PCSCD, NV_RAM_CSX_CNFG); 
    }

#endif

/*******************************************************************************
*
* sysNvRead - read one byte from NVRAM
*
* This routine reads a single byte from a specified offset in NVRAM.
*
* RETURNS: The byte from the specified NVRAM offset.
*/

UCHAR sysNvRead
    (
    ULONG	offset	/* NVRAM offset to read the byte from */
    )
    {
#if  defined(INCLUDE_NVRAM)
    sysOutByte (NV_RAM_MSB_REG, MSB(offset));
    sysOutByte (NV_RAM_LSB_REG, LSB(offset));
    return (sysInByte (NV_RAM_DAT_REG));
#endif /* INCLUDE_NVRAM */
    }

/*******************************************************************************
*
* sysNvWrite - write one byte to NVRAM
*
* This routine writes a single byte to a specified offset in NVRAM. 
*
* RETURNS: N/A
*/

void sysNvWrite
    (
    ULONG	offset,	/* NVRAM offset to write the byte to */
    UCHAR	data	/* datum byte */
    )
    {
#if  defined(INCLUDE_NVRAM)
    sysOutByte (NV_RAM_MSB_REG, MSB(offset));
    sysOutByte (NV_RAM_LSB_REG, LSB(offset));
    sysOutByte (NV_RAM_DAT_REG, data);
#endif /* INCLUDE_NVRAM */
    }

#ifdef	INCLUDE_FLASH
/*******************************************************************************
*
* sysFlashWriteEnable - enable writing to flash memory
*
* This routine enables writing to flash on the Sandpoint 
*
* RETURNS: N/A 
*
* SEE ALSO: sysFlashWriteDisable()
*/

void sysFlashWriteEnable (void)
    {
    ULONG tempLong;
    UCHAR tempChar;

    /* Enable flash Writes on MPC107 */

    tempLong = sys107RegRead (MPC107_PICR1_ADRS); 

    tempLong |= MPC107_FLASH_WRITE_BIT;

    sys107RegWrite (MPC107_PICR1_ADRS, tempLong); 

    /* Enable flash writes on Winbond */

    pciConfigInByte  (WB_PCI_BUS, WB_PCI_DEV, WB_PCI_FUNC, 
                      WB_CHIPSEL_CTRL_INDX, &tempChar);

    tempChar &= ~WB_FLASHWRITE_OFF;

    pciConfigOutByte (WB_PCI_BUS, WB_PCI_DEV, WB_PCI_FUNC,
                      WB_CHIPSEL_CTRL_INDX, tempChar);

    pciConfigInByte  (WB_PCI_BUS, WB_PCI_DEV, WB_PCI_FUNC, 
                      WB_CHIPSEL_CTRL_INDX, &tempChar);

    tempChar |= WB_EXT_BIOS_ENABLE;

    pciConfigOutByte (WB_PCI_BUS, WB_PCI_DEV, WB_PCI_FUNC,
                      WB_CHIPSEL_CTRL_INDX, tempChar);

 
    }


/*******************************************************************************
*
* sysFlashWriteDisable - disable writing to flash memory
*
* This routine disables writing to flash on the Sandpoint 
*
* RETURNS: N/A 
*
* SEE ALSO: sysFlashWriteEnable()
*/

void sysFlashWriteDisable (void)
    {
    ULONG tempLong;
    UCHAR tempChar;

    /* Disable flash Writes on MPC107 */

    tempLong = sys107RegRead (MPC107_PICR1_ADRS); 

    tempLong &= ~MPC107_FLASH_WRITE_BIT;

    sys107RegWrite (MPC107_PICR1_ADRS, tempLong); 

    /* Disable flash writes on winbond */

    pciConfigInByte  (WB_PCI_BUS, WB_PCI_DEV, WB_PCI_FUNC, 
                      WB_CHIPSEL_CTRL_INDX, &tempChar);

    tempChar |= WB_FLASHWRITE_OFF;

    pciConfigOutByte (WB_PCI_BUS, WB_PCI_DEV, WB_PCI_FUNC,
                      WB_CHIPSEL_CTRL_INDX, tempChar);

    pciConfigInByte  (WB_PCI_BUS, WB_PCI_DEV, WB_PCI_FUNC, 
                      WB_CHIPSEL_CTRL_INDX, &tempChar);

    tempChar &= ~WB_EXT_BIOS_ENABLE;

    pciConfigOutByte (WB_PCI_BUS, WB_PCI_DEV, WB_PCI_FUNC,
                      WB_CHIPSEL_CTRL_INDX, tempChar);
 
    }

/*******************************************************************************
*
* sysFlashBoardDelay - delay for 1 uSecs
*
* This routine will delay for 1 uSec  by counting
* PPC decrementer ticks.
*
* RETURNS: N/A
*/

void sysFlashBoardDelay
    (
    void
    )
    {
    FAST UINT oldval;               /* decrementer value */
    FAST UINT newval;               /* decrementer value */
    FAST UINT totalDelta;           /* Dec. delta for entire delay period */
    FAST UINT decElapsed;           /* cumulative decrementer ticks */

    /*
     * Calculate delt