📄 iodefine.h
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unsigned char b3 :1; /* DTON */
unsigned char b2 :1; /* MSON */
unsigned char b1 :1; /* SA */
unsigned char b0 :1; /* */
} BIT; /* */
}; /* */
union un_iegr { /* union IEGR */
unsigned char BYTE; /* Byte Access */
struct { /* Bit Access */
unsigned char :3; /* */
unsigned char IEG4:1; /* IEG4 */
unsigned char IEG3:1; /* IEG3 */
unsigned char IEG2:1; /* IEG2 */
unsigned char IEG1:1; /* IEG1 */
unsigned char IEG0:1; /* IEG0 */
} BIT; /* */
}; /* */
/* */
union un_ienr1 { /* union IENR1 */
unsigned char BYTE; /* Byte Access */
struct { /* Bit Access */
unsigned char IENTA:1; /* IENTA */
unsigned char IENS1:1; /* IENS1 */
unsigned char IENWP:1; /* IENWP */
unsigned char IEN4 :1; /* IEN4 */
unsigned char IEN3 :1; /* IEN3 */
unsigned char IEN2 :1; /* IEN2 */
unsigned char IEN1 :1; /* IEN1 */
unsigned char IEN0 :1; /* IEN0 */
} BIT; /* */
}; /* */
union un_ienr2 { /* union IENR2 */
unsigned char BYTE; /* Byte Access */
struct { /* Bit Access */
unsigned char IENDT :1; /* IENDT */
unsigned char IENAD :1; /* IENAD */
unsigned char :1; /* */
unsigned char IENTG :1; /* IENTG */
unsigned char IENTFH:1; /* IENTFH */
unsigned char IENTFL:1; /* IENTFL */
unsigned char IENTC :1; /* IENTC */
unsigned char IENEC :1; /* IENEC */
} BIT; /* */
}; /* */
union un_irr1 { /* union IRR1 */
unsigned char BYTE; /* Byte Access */
struct { /* Bit Access */
unsigned char IRRTA:1; /* IRRTA */
unsigned char IRRS1:1; /* IRRS1 */
unsigned char :1; /* */
unsigned char IRRI4:1; /* IRRI4 */
unsigned char IRRI3:1; /* IRRI3 */
unsigned char IRRI2:1; /* IRRI2 */
unsigned char IRRI1:1; /* IRRI1 */
unsigned char IRRI0:1; /* IRRI0 */
} BIT; /* */
}; /* */
union un_irr2 { /* union IRR2 */
unsigned char BYTE; /* Byte Access */
struct { /* Bit Access */
unsigned char IRRDT :1; /* IRRDT */
unsigned char IRRAD :1; /* IRRAD */
unsigned char :1; /* */
unsigned char IRRTG :1; /* IRRTG */
unsigned char IRRTFH:1; /* IRRTFH */
unsigned char IRRTFL:1; /* IRRTFL */
unsigned char IRRTC :1; /* IRRTC */
unsigned char IRREC :1; /* IRREC */
} BIT; /* */
};
union un_iwpr { /* union IWPR */
unsigned char BYTE; /* Byte Access */
struct { /* Bit Access */
unsigned char IWPF7:1; /* IWPF7 */
unsigned char IWPF6:1; /* IWPF6 */
unsigned char IWPF5:1; /* IWPF5 */
unsigned char IWPF4:1; /* IWPF4 */
unsigned char IWPF3:1; /* IWPF3 */
unsigned char IWPF2:1; /* IWPF2 */
unsigned char IWPF1:1; /* IWPF1 */
unsigned char IWPF0:1; /* IWPF0 */
} BIT; /* */
}; /* */
union un_ckstpr1 { /* union CKSTPR1*/
unsigned char BYTE; /* Byte Access */
struct { /* Bit Access */
unsigned char S1CKSTP :1; /* S1CKSTP */
unsigned char S31CKSTP:1; /* S31CKSTP */
unsigned char S32CKSTP:1; /* S32CKSTP */
unsigned char ADCKSTP :1; /* ADCKSTP */
unsigned char TGCKSTP :1; /* TGCKSTP */
unsigned char TFCKSTP :1; /* TFCKSTP */
unsigned char TCCKSTP :1; /* TCCKSTP */
unsigned char TACKSTP :1; /* TACKSTP */
} BIT; /* */
}; /* */
union un_ckstpr2 { /* union CKSTPR2*/
unsigned char BYTE; /* Byte Access */
struct { /* Bit Access */
unsigned char :4; /* */
unsigned char AECKSTP:1; /* AECKSTP */
unsigned char WDCKSTP:1; /* WDCKSTP */
unsigned char PWCKSTP:1; /* PWCKSTP */
unsigned char LDCKSTP:1; /* LDCKSTP */
} BIT; /* */
}; /* */
union set_ccr { /* struct CCR */
unsigned char BYTE; /* Byte Access */
struct { /* Bit Access */
unsigned char I:1; /* Interrupt Mask Bit*/
unsigned char U:1; /* User Bit */
unsigned char H:1; /* Half-Carry Flag */
unsigned char Us:1; /* User Bit */
unsigned char N:1; /* Negative Flag */
unsigned char Z:1; /* Zero Flag */
unsigned char V:1; /* Overflow Flag */
unsigned char C:1; /* Carry Flag */
} BIT; /* */
};
union set_tcsrw { /* struct TCSRW */
unsigned char BYTE; /* Byte Access */
struct { /* Bit Access */
unsigned char B6WI:1; /* Bit 6 write inhibit*/
unsigned char TCWE:1; /* Timer counter W write enable*/
unsigned char B4WI:1; /* Bit 4 write inhibit */
unsigned char TCSRWE:1; /* Timer control/status register W write enable*/
unsigned char B2WI:1; /* Bit 2 write inhibit */
unsigned char WDON:1; /* Watchdog timer on*/
unsigned char B0WI:1; /* Bit 0 write inhibit */
unsigned char WRST:1; /* Watchdog timer reset */
} BIT; /* */
}; /* */
#define AEC (*(volatile struct st_aec *)0xFF95) /* AEC Address*/
#define SCI1 (*(volatile struct st_sci1 *)0xFFA0) /* SCI1 Address*/
#define SCI31 (*(volatile struct st_sci3 *)0xFF98) /* SCI31 Address*/
#define SCI32 (*(volatile struct st_sci3 *)0xFFA8) /* SCI32 Address*/
#define TMRA (*(volatile struct st_tmra *)0xFFB0) /* TMRA Address*/
#define WDT (*(volatile struct st_wdt *)0xFFB2) /* WDT Address*/
#define TMRC (*(volatile struct st_tmrc *)0xFFB4) /* TMRC Address*/
#define TMRF (*(volatile struct st_tmrf *)0xFFB6) /* TMRF Address*/
#define TMRG (*(volatile struct st_tmrg *)0xFFBC) /* TMRG Address*/
#define LCD (*(volatile struct st_lcd *)0xFFC1) /* LCD Address*/
#define AD (*(volatile struct st_ad *)0xFFC4) /* A/D Address*/
#define PWM (*(volatile struct st_pwm *)0xFFD0) /* PWM Address*/
#define IO (*(volatile struct st_io *)0xFFC8) /* IO Address*/
#define WEGR (*(volatile union un_wegr *)0xFF90) /* WEGR Address*/
#define SPCR (*(volatile union un_spcr *)0xFF91) /* SPCR Address*/
#define CWOSR (*(volatile union un_cwosr *)0xFF92) /* CWOSR Address*/
#define SYSCR1 (*(volatile union un_syscr1*)0xFFF0) /* SYSCR1Address*/
#define SYSCR2 (*(volatile union un_syscr2*)0xFFF1) /* SYSCR2Address*/
#define IEGR (*(volatile union un_iegr *)0xFFF2) /* IEGR Address*/
#define IENR1 (*(volatile union un_ienr1 *)0xFFF3) /* IENR1 Address*/
#define IENR2 (*(volatile union un_ienr2 *)0xFFF4) /* IENR2 Address*/
#define IRR1 (*(volatile union un_irr1 *)0xFFF6) /* IRR1 Address*/
#define IRR2 (*(volatile union un_irr2 *)0xFFF7) /* IRR2 Address*/
#define IWPR (*(volatile union un_iwpr *)0xFFF9) /* IWPR Address*/
#define IWPR (*(volatile union un_iwpr *)0xFFF9) /* IWPR Address*/
#define CKSTPR1 (*(volatile union un_ckstpr1*)0xFFFA) /* CKSTPR1 Address*/
#define CKSTPR2 (*(volatile union un_ckstpr2*)0xFFFB) /* CKSTPR2 Address*/
#define TLC TCC /* Change TLC --> TCC */
#define CCR (*(volatile union set_ccr *)0xFFFC) /* CCR Address*/
#define TCSRW (*(volatile union set_tcsrw *)0xFFFD) /* TCSRW Address*/
#define LCDRAM (volatile unsigned char *)0xF740 /* LCD RAM */
#define p5 IO.PDR5.BYTE /* IO port 5 data register */
#define p6 IO.PDR6.BYTE /* IO port 6 data register */
#define p7 IO.PDR7.BYTE /* IO port 7 data register */
#define p8 IO.PDR8.BYTE /* IO port 8 data register */
#define p9 IO.PDR9.BYTE /* IO port 9 data register */
#define pa IO.PDRA.BYTE /* IO port A data register */
#define pc5 IO.PCR5 /* IO port 5 control register */
#define pc6 IO.PCR6 /* IO port 6 control register */
#define pc7 IO.PCR7 /* IO port 7 control register */
#define pc8 IO.PCR8 /* IO port 8 control register */
#define pc9 IO.PCR9 /* IO port 9 control register */
#define pca IO.PCRA /* IO port A control register */
#endif /* IODEFINE_H_INCLUDED */
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