📄 ias_stateflow_rev_a.mdl
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OutDataTypeMode "Inherit via internal rule"
OutDataType "sfix(16)"
OutScaling "2^0"
SaturateOnIntegerOverflow off
}
Block {
BlockType Product
Name "Product1"
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CollapseMode "All dimensions"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutDataType "sfix(16)"
OutScaling "2^0"
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BlockType Product
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InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutDataType "sfix(16)"
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Block {
BlockType Sum
Name "Subtract"
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Position [210, 252, 240, 283]
Inputs "+-"
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InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutDataType "sfix(16)"
OutScaling "2^-10"
SaturateOnIntegerOverflow off
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Block {
BlockType Sum
Name "Subtract1"
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Inputs "+-"
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InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutDataType "sfix(16)"
OutScaling "2^-10"
SaturateOnIntegerOverflow off
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Block {
BlockType Sum
Name "Sum"
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Position [335, 35, 355, 55]
ShowName off
IconShape "round"
Inputs "|++"
CollapseMode "All dimensions"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutDataType "sfix(16)"
OutScaling "2^0"
SaturateOnIntegerOverflow off
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Block {
BlockType Constant
Name "gamma"
Position [20, 216, 60, 234]
Value "1.4"
OutDataTypeMode "Inherit via back propagation"
OutDataType "sfix(16)"
OutScaling "2^0"
Port {
PortNumber 1
Name "gamma"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
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}
Block {
BlockType Outport
Name "Vc"
Position [835, 83, 865, 97]
IconDisplay "Port number"
}
Line {
SrcBlock "qc"
SrcPort 1
DstBlock "Pressure Conversion1"
DstPort 1
}
Line {
SrcBlock "P0"
SrcPort 1
DstBlock "Pressure Conversion"
DstPort 1
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Line {
Name "P0"
Labels [0, 0]
SrcBlock "Pressure Conversion"
SrcPort 1
Points [70, 0]
Branch {
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DstBlock "Product1"
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Branch {
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DstBlock "Divide2"
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Name "qc"
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SrcBlock "Pressure Conversion1"
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DstBlock "Divide2"
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Name "gamma"
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SrcBlock "gamma"
SrcPort 1
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Branch {
Points [45, 0]
Branch {
Points [145, 0]
DstBlock "Product"
DstPort 2
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Branch {
Points [0, 35]
DstBlock "Subtract"
DstPort 1
}
}
Branch {
Points [0, 85]
DstBlock "Divide4"
DstPort 2
}
}
Line {
SrcBlock "Density"
SrcPort 1
Points [20, 0]
DstBlock "D"
DstPort 1
}
Line {
SrcBlock "Cte"
SrcPort 1
Points [5, 0]
DstBlock "Product"
DstPort 1
}
Line {
SrcBlock "Constant"
SrcPort 1
Points [0, -5]
DstBlock "Subtract"
DstPort 2
}
Line {
SrcBlock "Product"
SrcPort 1
Points [0, 30]
DstBlock "Divide"
DstPort 1
}
Line {
SrcBlock "Subtract"
SrcPort 1
Points [25, 0]
Branch {
Points [20, 0; 0, -10]
DstBlock "Divide"
DstPort 2
}
Branch {
Points [0, 25]
DstBlock "Divide4"
DstPort 1
}
}
Line {
SrcBlock "Divide"
SrcPort 1
DstBlock "Product1"
DstPort 2
}
Line {
SrcBlock "Product1"
SrcPort 1
Points [0, -35]
DstBlock "Divide1"
DstPort 1
}
Line {
Name "Density"
Labels [0, 0]
SrcBlock "D"
SrcPort 1
Points [290, 0; 0, 45]
DstBlock "Divide1"
DstPort 2
}
Line {
SrcBlock "Divide2"
SrcPort 1
DstBlock "Sum"
DstPort 1
}
Line {
SrcBlock "Constant1"
SrcPort 1
Points [45, 0]
DstBlock "Sum"
DstPort 2
}
Line {
SrcBlock "Sum"
SrcPort 1
DstBlock "Math\nFunction"
DstPort 1
}
Line {
SrcBlock "Divide4"
SrcPort 1
Points [145, 0; 0, -245]
DstBlock "Math\nFunction"
DstPort 2
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Line {
SrcBlock "Math\nFunction"
SrcPort 1
DstBlock "Subtract1"
DstPort 1
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Line {
SrcBlock "Constant2"
SrcPort 1
Points [15, 0; 0, -45]
DstBlock "Subtract1"
DstPort 2
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Line {
SrcBlock "Divide1"
SrcPort 1
Points [200, 0]
DstBlock "Product2"
DstPort 2
}
Line {
SrcBlock "Subtract1"
SrcPort 1
Points [5, 0; 0, 15]
DstBlock "Product2"
DstPort 1
}
Line {
SrcBlock "Product2"
SrcPort 1
DstBlock "Math\nFunction1"
DstPort 1
}
Line {
SrcBlock "Math\nFunction1"
SrcPort 1
DstBlock "Vc"
DstPort 1
}
}
}
Block {
BlockType Reference
Name "Compare\nTo Zero"
Ports [1, 1]
Position [525, 125, 555, 155]
SourceBlock "simulink/Logic and Bit\nOperations/Compare\nTo Zero"
SourceType "Compare To Zero"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
relop "<="
LogicOutDataTypeMode "uint8"
ZeroCross off
}
Block {
BlockType DigitalClock
Name "Digital Clock"
Position [15, 143, 80, 167]
SampleTime "0.01"
}
Block {
BlockType SubSystem
Name "IAS"
Ports [2, 1]
Position [475, 30, 530, 110]
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
System {
Name "IAS"
Location [689, 210, 1229, 415]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "Density"
Position [25, 38, 55, 52]
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Block {
BlockType Inport
Name "qc"
Position [30, 103, 60, 117]
Port "2"
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
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Block {
BlockType Constant
Name "Constant"
Position [200, 65, 230, 95]
Value "2"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Block {
BlockType Reference
Name "D"
Ports [1, 1]
Position [90, 28, 150, 62]
SourceBlock "aerolibconvert2/Density Conversion"
SourceType "Density Conversion"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
IU "kg/m^3"
OU "kg/m^3"
Port {
PortNumber 1
Name "Density"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Product
Name "Divide4"
Ports [2, 1]
Position [350, 122, 380, 153]
Inputs "*/"
CollapseMode "All dimensions"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutDataType "sfix(16)"
OutScaling "2^-10"
RndMeth "Floor"
SaturateOnIntegerOverflow off
}
Block {
BlockType Math
Name "Math\nFunction"
Ports [1, 1]
Position [410, 124, 440, 156]
Operator "sqrt"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Block {
BlockType Reference
Name "Pressure Conversion2"
Ports [1, 1]
Position [100, 94, 140, 126]
ShowName off
SourceBlock "aerolibconvert2/Pressure Conversion"
SourceType "Pressure Conversion"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
IU "Pa"
OU "Pa"
Port {
PortNumber 1
Name "qc"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Product
Name "Product"
Ports [2, 1]
Position [265, 87, 295, 118]
CollapseMode "All dimensions"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutDataType "sfix(16)"
OutScaling "2^0"
SaturateOnIntegerOverflow off
}
Block {
BlockType Outport
Name "Vi"
Position [485, 133, 515, 147]
IconDisplay "Port number"
}
Line {
SrcBlock "qc"
SrcPort 1
DstBlock "Pressure Conversion2"
DstPort 1
}
Line {
SrcBlock "Density"
SrcPort 1
DstBlock "D"
DstPort 1
}
Line {
Name "qc"
Labels [0, 0]
SrcBlock "Pressure Conversion2"
SrcPort 1
DstBlock "Product"
DstPort 2
}
Line {
SrcBlock "Constant"
SrcPort 1
Points [5, 0; 0, 15]
DstBlock "Product"
DstPort 1
}
Line {
SrcBlock "Product"
SrcPort 1
Points [15, 0; 0, 25]
DstBlock "Divide4"
DstPort 1
}
Line {
SrcBlock "Divide4"
SrcPort 1
DstBlock "Math\nFunction"
DstPort 1
}
Line {
SrcBlock "Math\nFunction"
SrcPort 1
DstBlock "Vi"
DstPort 1
}
Line {
Name "Density"
Labels [0, 0]
SrcBlock "D"
SrcPort 1
Points [175, 0; 0, 100]
DstBlock "Divide4"
DstPort 2
}
}
}
Block {
BlockType SubSystem
Name "IAS_CAS_Statechart"
Ports [1, 1]
Position [225, 106, 345, 204]
PermitHierarchicalResolution "ExplicitOnly"
MinAlgLoopOccurrences off
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