📄 main.dbg
字号:
;*** SYNR - CRG Synthesizer Register; 0x00000034 ***
SYNR: equ $00000034 ;*** SYNR - CRG Synthesizer Register; 0x00000034 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SYNR_SYN0: equ 0 ; CRG Synthesizer Bit 0
SYNR_SYN1: equ 1 ; CRG Synthesizer Bit 1
SYNR_SYN2: equ 2 ; CRG Synthesizer Bit 2
SYNR_SYN3: equ 3 ; CRG Synthesizer Bit 3
SYNR_SYN4: equ 4 ; CRG Synthesizer Bit 4
SYNR_SYN5: equ 5 ; CRG Synthesizer Bit 5
; bit position masks
mSYNR_SYN0: equ %00000001
mSYNR_SYN1: equ %00000010
mSYNR_SYN2: equ %00000100
mSYNR_SYN3: equ %00001000
mSYNR_SYN4: equ %00010000
mSYNR_SYN5: equ %00100000
;*** REFDV - CRG Reference Divider Register; 0x00000035 ***
REFDV: equ $00000035 ;*** REFDV - CRG Reference Divider Register; 0x00000035 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
REFDV_REFDV0: equ 0 ; CRG Reference Divider Bit 0
REFDV_REFDV1: equ 1 ; CRG Reference Divider Bit 1
REFDV_REFDV2: equ 2 ; CRG Reference Divider Bit 2
REFDV_REFDV3: equ 3 ; CRG Reference Divider Bit 3
; bit position masks
mREFDV_REFDV0: equ %00000001
mREFDV_REFDV1: equ %00000010
mREFDV_REFDV2: equ %00000100
mREFDV_REFDV3: equ %00001000
;*** CRGFLG - CRG Flags Register; 0x00000037 ***
CRGFLG: equ $00000037 ;*** CRGFLG - CRG Flags Register; 0x00000037 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
CRGFLG_SCM: equ 0 ; Self-clock mode Status
CRGFLG_SCMIF: equ 1 ; Self-clock mode Interrupt Flag
CRGFLG_TRACK: equ 2 ; Track Status
CRGFLG_LOCK: equ 3 ; Lock Status
CRGFLG_LOCKIF: equ 4 ; PLL Lock Interrupt Flag
CRGFLG_PORF: equ 6 ; Power on Reset Flag
CRGFLG_RTIF: equ 7 ; Real Time Interrupt Flag
; bit position masks
mCRGFLG_SCM: equ %00000001
mCRGFLG_SCMIF: equ %00000010
mCRGFLG_TRACK: equ %00000100
mCRGFLG_LOCK: equ %00001000
mCRGFLG_LOCKIF: equ %00010000
mCRGFLG_PORF: equ %01000000
mCRGFLG_RTIF: equ %10000000
;*** CRGINT - CRG Interrupt Enable Register; 0x00000038 ***
CRGINT: equ $00000038 ;*** CRGINT - CRG Interrupt Enable Register; 0x00000038 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
CRGINT_SCMIE: equ 1 ; Self-clock mode Interrupt Enable
CRGINT_LOCKIE: equ 4 ; Lock Interrupt Enable
CRGINT_RTIE: equ 7 ; Real Time Interrupt Enable
; bit position masks
mCRGINT_SCMIE: equ %00000010
mCRGINT_LOCKIE: equ %00010000
mCRGINT_RTIE: equ %10000000
;*** CLKSEL - CRG Clock Select Register; 0x00000039 ***
CLKSEL: equ $00000039 ;*** CLKSEL - CRG Clock Select Register; 0x00000039 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
CLKSEL_COPWAI: equ 0 ; COP stops in WAIT mode
CLKSEL_RTIWAI: equ 1 ; RTI stops in WAIT mode
CLKSEL_CWAI: equ 2 ; CLK24 and CLK23 stop in WAIT mode
CLKSEL_PLLWAI: equ 3 ; PLL stops in WAIT mode
CLKSEL_ROAWAI: equ 4 ; Reduced Oscillator Amplitude in WAIT mode
CLKSEL_SYSWAI: equ 5 ; System clocks stop in WAIT mode
CLKSEL_PSTP: equ 6 ; Pseudo Stop
CLKSEL_PLLSEL: equ 7 ; PLL selected for system clock
; bit position masks
mCLKSEL_COPWAI: equ %00000001
mCLKSEL_RTIWAI: equ %00000010
mCLKSEL_CWAI: equ %00000100
mCLKSEL_PLLWAI: equ %00001000
mCLKSEL_ROAWAI: equ %00010000
mCLKSEL_SYSWAI: equ %00100000
mCLKSEL_PSTP: equ %01000000
mCLKSEL_PLLSEL: equ %10000000
;*** PLLCTL - CRG PLL Control Register; 0x0000003A ***
PLLCTL: equ $0000003A ;*** PLLCTL - CRG PLL Control Register; 0x0000003A ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PLLCTL_SCME: equ 0 ; Self-clock mode enable
PLLCTL_PCE: equ 1 ; COP Enable during Pseudo Stop Bit
PLLCTL_PRE: equ 2 ; RTI Enable during Pseudo Stop Bit
PLLCTL_ACQ: equ 4 ; Acquisition
PLLCTL_AUTO: equ 5 ; Automatic Bandwidth Control
PLLCTL_PLLON: equ 6 ; Phase Lock Loop On
PLLCTL_CME: equ 7 ; Crystal Monitor Enable
; bit position masks
mPLLCTL_SCME: equ %00000001
mPLLCTL_PCE: equ %00000010
mPLLCTL_PRE: equ %00000100
mPLLCTL_ACQ: equ %00010000
mPLLCTL_AUTO: equ %00100000
mPLLCTL_PLLON: equ %01000000
mPLLCTL_CME: equ %10000000
;*** RTICTL - CRG RTI Control Register; 0x0000003B ***
RTICTL: equ $0000003B ;*** RTICTL - CRG RTI Control Register; 0x0000003B ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
RTICTL_RTR0: equ 0 ; Real Time Interrupt Modulus Counter Select Bit 0
RTICTL_RTR1: equ 1 ; Real Time Interrupt Modulus Counter Select Bit 1
RTICTL_RTR2: equ 2 ; Real Time Interrupt Modulus Counter Select Bit 2
RTICTL_RTR3: equ 3 ; Real Time Interrupt Modulus Counter Select Bit 3
RTICTL_RTR4: equ 4 ; Real Time Interrupt Prescale Rate Select Bit 4
RTICTL_RTR5: equ 5 ; Real Time Interrupt Prescale Rate Select Bit 5
RTICTL_RTR6: equ 6 ; Real Time Interrupt Prescale Rate Select Bit 6
; bit position masks
mRTICTL_RTR0: equ %00000001
mRTICTL_RTR1: equ %00000010
mRTICTL_RTR2: equ %00000100
mRTICTL_RTR3: equ %00001000
mRTICTL_RTR4: equ %00010000
mRTICTL_RTR5: equ %00100000
mRTICTL_RTR6: equ %01000000
;*** COPCTL - CRG COP Control Register; 0x0000003C ***
COPCTL: equ $0000003C ;*** COPCTL - CRG COP Control Register; 0x0000003C ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
COPCTL_CR0: equ 0 ; COP Watchdog Timer Rate select Bit 0
COPCTL_CR1: equ 1 ; COP Watchdog Timer Rate select Bit 1
COPCTL_CR2: equ 2 ; COP Watchdog Timer Rate select Bit 2
COPCTL_RSBCK: equ 6 ; COP and RTI stop in Active BDM mode Bit
COPCTL_WCOP: equ 7 ; Window COP mode
; bit position masks
mCOPCTL_CR0: equ %00000001
mCOPCTL_CR1: equ %00000010
mCOPCTL_CR2: equ %00000100
mCOPCTL_RSBCK: equ %01000000
mCOPCTL_WCOP: equ %10000000
;*** ARMCOP - CRG COP Timer Arm/Reset Register; 0x0000003F ***
ARMCOP: equ $0000003F ;*** ARMCOP - CRG COP Timer Arm/Reset Register; 0x0000003F ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ARMCOP_BIT0: equ 0 ; CRG COP Timer Arm/Reset Bit 0
ARMCOP_BIT1: equ 1 ; CRG COP Timer Arm/Reset Bit 1
ARMCOP_BIT2: equ 2 ; CRG COP Timer Arm/Reset Bit 2
ARMCOP_BIT3: equ 3 ; CRG COP Timer Arm/Reset Bit 3
ARMCOP_BIT4: equ 4 ; CRG COP Timer Arm/Reset Bit 4
ARMCOP_BIT5: equ 5 ; CRG COP Timer Arm/Reset Bit 5
ARMCOP_BIT6: equ 6 ; CRG COP Timer Arm/Reset Bit 6
ARMCOP_BIT7: equ 7 ; CRG COP Timer Arm/Reset Bit 7
; bit position masks
mARMCOP_BIT0: equ %00000001
mARMCOP_BIT1: equ %00000010
mARMCOP_BIT2: equ %00000100
mARMCOP_BIT3: equ %00001000
mARMCOP_BIT4: equ %00010000
mARMCOP_BIT5: equ %00100000
mARMCOP_BIT6: equ %01000000
mARMCOP_BIT7: equ %10000000
;*** TIOS - Timer Input Capture/Output Compare Select; 0x00000040 ***
TIOS: equ $00000040 ;*** TIOS - Timer Input Capture/Output Compare Select; 0x00000040 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TIOS_IOS0: equ 0 ; Input Capture or Output Compare Channel Configuration Bit 0
TIOS_IOS1: equ 1 ; Input Capture or Output Compare Channel Configuration Bit 1
TIOS_IOS2: equ 2 ; Input Capture or Output Compare Channel Configuration Bit 2
TIOS_IOS3: equ 3 ; Input Capture or Output Compare Channel Configuration Bit 3
TIOS_IOS4: equ 4 ; Input Capture or Output Compare Channel Configuration Bit 4
TIOS_IOS5: equ 5 ; Input Capture or Output Compare Channel Configuration Bit 5
TIOS_IOS6: equ 6 ; Input Capture or Output Compare Channel Configuration Bit 6
TIOS_IOS7: equ 7 ; Input Capture or Output Compare Channel Configuration Bit 7
; bit position masks
mTIOS_IOS0: equ %00000001
mTIOS_IOS1: equ %00000010
mTIOS_IOS2: equ %00000100
mTIOS_IOS3: equ %00001000
mTIOS_IOS4: equ %00010000
mTIOS_IOS5: equ %00100000
mTIOS_IOS6: equ %01000000
mTIOS_IOS7: equ %10000000
;*** CFORC - Timer Compare Force Register; 0x00000041 ***
CFORC: equ $00000041 ;*** CFORC - Timer Compare Force Register; 0x00000041 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
CFORC_FOC0: equ 0 ; Force Output Compare Action for Channel 0
CFORC_FOC1: equ 1 ; Force Output Compare Action for Channel 1
CFORC_FOC2: equ 2 ; Force Output Compare Action for Channel 2
CFORC_FOC3: equ 3 ; Force Output Compare Action for Channel 3
CFORC_FOC4: equ 4 ; Force Output Compare Action for Channel 4
CFORC_FOC5: equ 5 ; Force Output Compare Action for Channel 5
CFORC_FOC6: equ 6 ; Force Output Compare Action for Channel 6
CFORC_FOC7: equ 7 ; Force Output Compare Action for Channel 7
; bit position masks
mCFORC_FOC0: equ %00000001
mCFORC_FOC1: equ %00000010
mCFORC_FOC2: equ %00000100
mCFORC_FOC3: equ %00001000
mCFORC_FOC4: equ %00010000
mCFORC_FOC5: equ %00100000
mCFORC_FOC6: equ %01000000
mCFORC_FOC7: equ %10000000
;*** OC7M - Output Compare 7 Mask Register; 0x00000042 ***
OC7M: equ $00000042 ;*** OC7M - Output Compare 7 Mask Register; 0x00000042 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
OC7M_OC7M0: equ 0 ; Output Compare 7 Mask Bit 0
OC7M_OC7M1: equ 1 ; Output Compare 7 Mask Bit 1
OC7M_OC7M2: equ 2 ; Output Compare 7 Mask Bit 2
OC7M_OC7M3: equ 3 ; Output Compare 7 Mask Bit 3
OC7M_OC7M4: equ 4 ; Output Compare 7 Mask Bit 4
OC7M_OC7M5: equ 5 ; Output Compare 7 Mask Bit 5
OC7M_OC7M6: equ 6 ; Output Compare 7 Mask Bit 6
OC7M_OC7M7: equ 7 ⌨️ 快捷键说明
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