📄 main.dbg
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INITRG_REG11: equ 3 ; Internal Registers Map Position Bit 11
INITRG_REG12: equ 4 ; Internal Registers Map Position Bit 12
INITRG_REG13: equ 5 ; Internal Registers Map Position Bit 13
INITRG_REG14: equ 6 ; Internal Registers Map Position Bit 14
; bit position masks
mINITRG_REG11: equ %00001000
mINITRG_REG12: equ %00010000
mINITRG_REG13: equ %00100000
mINITRG_REG14: equ %01000000
;*** INITEE - Initialization of Internal EEPROM Position Register; 0x00000012 ***
INITEE: equ $00000012 ;*** INITEE - Initialization of Internal EEPROM Position Register; 0x00000012 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
INITEE_EEON: equ 0 ; Internal EEPROM On
INITEE_EE12: equ 4 ; Internal EEPROM map position Bit 12
INITEE_EE13: equ 5 ; Internal EEPROM map position Bit 13
INITEE_EE14: equ 6 ; Internal EEPROM map position Bit 14
INITEE_EE15: equ 7 ; Internal EEPROM map position Bit 15
; bit position masks
mINITEE_EEON: equ %00000001
mINITEE_EE12: equ %00010000
mINITEE_EE13: equ %00100000
mINITEE_EE14: equ %01000000
mINITEE_EE15: equ %10000000
;*** MISC - Miscellaneous System Control Register; 0x00000013 ***
MISC: equ $00000013 ;*** MISC - Miscellaneous System Control Register; 0x00000013 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
MISC_ROMON: equ 0 ; Enable Flash EEPROM
MISC_ROMHM: equ 1 ; Flash EEPROM only in second half of memory map
MISC_EXSTR0: equ 2 ; External Access Stretch Bit 0
MISC_EXSTR1: equ 3 ; External Access Stretch Bit 1
; bit position masks
mMISC_ROMON: equ %00000001
mMISC_ROMHM: equ %00000010
mMISC_EXSTR0: equ %00000100
mMISC_EXSTR1: equ %00001000
;*** ITCR - Interrupt Test Control Register; 0x00000015 ***
ITCR: equ $00000015 ;*** ITCR - Interrupt Test Control Register; 0x00000015 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ITCR_ADR0: equ 0 ; Test register select Bit 0
ITCR_ADR1: equ 1 ; Test register select Bit 1
ITCR_ADR2: equ 2 ; Test register select Bit 2
ITCR_ADR3: equ 3 ; Test register select Bit 3
ITCR_WRTINT: equ 4 ; Write to the Interrupt Test Registers
; bit position masks
mITCR_ADR0: equ %00000001
mITCR_ADR1: equ %00000010
mITCR_ADR2: equ %00000100
mITCR_ADR3: equ %00001000
mITCR_WRTINT: equ %00010000
;*** ITEST - Interrupt Test Register; 0x00000016 ***
ITEST: equ $00000016 ;*** ITEST - Interrupt Test Register; 0x00000016 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ITEST_INT0: equ 0 ; Interrupt Test Register Bit 0
ITEST_INT2: equ 1 ; Interrupt Test Register Bit 1
ITEST_INT4: equ 2 ; Interrupt Test Register Bit 2
ITEST_INT6: equ 3 ; Interrupt Test Register Bit 3
ITEST_INT8: equ 4 ; Interrupt Test Register Bit 4
ITEST_INTA: equ 5 ; Interrupt Test Register Bit 5
ITEST_INTC: equ 6 ; Interrupt Test Register Bit 6
ITEST_INTE: equ 7 ; Interrupt Test Register Bit 7
; bit position masks
mITEST_INT0: equ %00000001
mITEST_INT2: equ %00000010
mITEST_INT4: equ %00000100
mITEST_INT6: equ %00001000
mITEST_INT8: equ %00010000
mITEST_INTA: equ %00100000
mITEST_INTC: equ %01000000
mITEST_INTE: equ %10000000
;*** PARTID - Part ID Register; 0x0000001A ***
PARTID: equ $0000001A ;*** PARTID - Part ID Register; 0x0000001A ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PARTID_ID0: equ 0 ; Part ID Register Bit 0
PARTID_ID1: equ 1 ; Part ID Register Bit 1
PARTID_ID2: equ 2 ; Part ID Register Bit 2
PARTID_ID3: equ 3 ; Part ID Register Bit 3
PARTID_ID4: equ 4 ; Part ID Register Bit 4
PARTID_ID5: equ 5 ; Part ID Register Bit 5
PARTID_ID6: equ 6 ; Part ID Register Bit 6
PARTID_ID7: equ 7 ; Part ID Register Bit 7
PARTID_ID8: equ 8 ; Part ID Register Bit 8
PARTID_ID9: equ 9 ; Part ID Register Bit 9
PARTID_ID10: equ 10 ; Part ID Register Bit 10
PARTID_ID11: equ 11 ; Part ID Register Bit 11
PARTID_ID12: equ 12 ; Part ID Register Bit 12
PARTID_ID13: equ 13 ; Part ID Register Bit 13
PARTID_ID14: equ 14 ; Part ID Register Bit 14
PARTID_ID15: equ 15 ; Part ID Register Bit 15
; bit position masks
mPARTID_ID0: equ %00000001
mPARTID_ID1: equ %00000010
mPARTID_ID2: equ %00000100
mPARTID_ID3: equ %00001000
mPARTID_ID4: equ %00010000
mPARTID_ID5: equ %00100000
mPARTID_ID6: equ %01000000
mPARTID_ID7: equ %10000000
mPARTID_ID8: equ %100000000
mPARTID_ID9: equ %1000000000
mPARTID_ID10: equ %10000000000
mPARTID_ID11: equ %100000000000
mPARTID_ID12: equ %1000000000000
mPARTID_ID13: equ %10000000000000
mPARTID_ID14: equ %100000000000000
mPARTID_ID15: equ %1000000000000000
;*** PARTIDH - Part ID Register High; 0x0000001A ***
PARTIDH: equ $0000001A ;*** PARTIDH - Part ID Register High; 0x0000001A ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PARTIDH_ID8: equ 0 ; Part ID Register Bit 8
PARTIDH_ID9: equ 1 ; Part ID Register Bit 9
PARTIDH_ID10: equ 2 ; Part ID Register Bit 10
PARTIDH_ID11: equ 3 ; Part ID Register Bit 11
PARTIDH_ID12: equ 4 ; Part ID Register Bit 12
PARTIDH_ID13: equ 5 ; Part ID Register Bit 13
PARTIDH_ID14: equ 6 ; Part ID Register Bit 14
PARTIDH_ID15: equ 7 ; Part ID Register Bit 15
; bit position masks
mPARTIDH_ID8: equ %00000001
mPARTIDH_ID9: equ %00000010
mPARTIDH_ID10: equ %00000100
mPARTIDH_ID11: equ %00001000
mPARTIDH_ID12: equ %00010000
mPARTIDH_ID13: equ %00100000
mPARTIDH_ID14: equ %01000000
mPARTIDH_ID15: equ %10000000
;*** PARTIDL - Part ID Register Low; 0x0000001B ***
PARTIDL: equ $0000001B ;*** PARTIDL - Part ID Register Low; 0x0000001B ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PARTIDL_ID0: equ 0 ; Part ID Register Bit 0
PARTIDL_ID1: equ 1 ; Part ID Register Bit 1
PARTIDL_ID2: equ 2 ; Part ID Register Bit 2
PARTIDL_ID3: equ 3 ; Part ID Register Bit 3
PARTIDL_ID4: equ 4 ; Part ID Register Bit 4
PARTIDL_ID5: equ 5 ; Part ID Register Bit 5
PARTIDL_ID6: equ 6 ; Part ID Register Bit 6
PARTIDL_ID7: equ 7 ; Part ID Register Bit 7
; bit position masks
mPARTIDL_ID0: equ %00000001
mPARTIDL_ID1: equ %00000010
mPARTIDL_ID2: equ %00000100
mPARTIDL_ID3: equ %00001000
mPARTIDL_ID4: equ %00010000
mPARTIDL_ID5: equ %00100000
mPARTIDL_ID6: equ %01000000
mPARTIDL_ID7: equ %10000000
;*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***
MEMSIZ0: equ $0000001C ;*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
MEMSIZ0_ram_sw0: equ 0 ; Allocated System RAM Memory Space Bit 0
MEMSIZ0_ram_sw1: equ 1 ; Allocated System RAM Memory Space Bit 1
MEMSIZ0_ram_sw2: equ 2 ; Allocated System RAM Memory Space Bit 2
MEMSIZ0_eep_sw0: equ 4 ; Allocated EEPROM Memory Space Bit 0
MEMSIZ0_eep_sw1: equ 5 ; Allocated EEPROM Memory Space Bit 1
MEMSIZ0_reg_sw0: equ 7 ; Allocated System Register Space
; bit position masks
mMEMSIZ0_ram_sw0: equ %00000001
mMEMSIZ0_ram_sw1: equ %00000010
mMEMSIZ0_ram_sw2: equ %00000100
mMEMSIZ0_eep_sw0: equ %00010000
mMEMSIZ0_eep_sw1: equ %00100000
mMEMSIZ0_reg_sw0: equ %10000000
;*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***
MEMSIZ1: equ $0000001D ;*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
MEMSIZ1_pag_sw0: equ 0 ; Allocated Off-Chip Memory Options Bit 0
MEMSIZ1_pag_sw1: equ 1 ; Allocated Off-Chip Memory Options Bit 1
MEMSIZ1_rom_sw0: equ 6 ; Allocated Flash EEPROM/ROM Physical Memory Space Bit 0
MEMSIZ1_rom_sw1: equ 7 ; Allocated Flash EEPROM/ROM Physical Memory Space Bit 1
; bit position masks
mMEMSIZ1_pag_sw0: equ %00000001
mMEMSIZ1_pag_sw1: equ %00000010
mMEMSIZ1_rom_sw0: equ %01000000
mMEMSIZ1_rom_sw1: equ %10000000
;*** INTCR - Interrupt Control Register; 0x0000001E ***
INTCR: equ $0000001E ;*** INTCR - Interrupt Control Register; 0x0000001E ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
INTCR_IRQEN: equ 6 ; External IRQ Enable
INTCR_IRQE: equ 7 ; IRQ Select Edge Sensitive Only
; bit position masks
mINTCR_IRQEN: equ %01000000
mINTCR_IRQE: equ %10000000
;*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***
HPRIO: equ $0000001F ;*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
HPRIO_PSEL1: equ 1 ; Highest Priority I Interrupt Bit 1
HPRIO_PSEL2: equ 2 ; Highest Priority I Interrupt Bit 2
HPRIO_PSEL3: equ 3 ; Highest Priority I Interrupt Bit 3
HPRIO_PSEL4: equ 4 ; Highest Priority I Interrupt Bit 4
HPRIO_PSEL5: equ 5 ; Highest Priority I Interrupt Bit 5
HPRIO_PSEL6: equ 6 ; Highest Priority I Interrupt Bit 6
HPRIO_PSEL7: equ 7 ; Highest Priority I Interrupt Bit 7
; bit position masks
mHPRIO_PSEL1: equ %00000010
mHPRIO_PSEL2: equ %00000100
mHPRIO_PSEL3: equ %00001000
mHPRIO_PSEL4: equ %00010000
mHPRIO_PSEL5: equ %00100000
mHPRIO_PSEL6: equ %01000000
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