📄 smckxd.inc
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APS2Base equ 0100h
TMRATE8 equ APS2Base+0000h ; RAM:ADC input settling time
UnStickPtr equ APS2Base+0001h ; RAM:Ptr to key that aborted Fn sticky state
QLENTSK equ APS2Base+0002h ; RAM:Quick Lock Enabled Task storage
QLDSTSK equ APS2Base+0003h ; RAM:Quick Lock Disabled Task storage
P1DATA equ APS2Base+0004h ; RAM:Emulated 8042 Port1 Data
RESMID equ APS2Base+0005h ; RAM:resume ID
RESMTSK equ APS2Base+0006h ; RAM:resume task
PBOverTL equ APS2Base+0007h ; RAM:Power button overrid timer low
PBOverTH equ APS2Base+0008h ; RAM:Power button overrid timer high
DELAY2 equ APS2Base+0009h ; DELAY2 variable
DELAY1 equ APS2Base+000Ah ; DELAY1 variable
X2TSK equ APS2Base+000Bh ; Dual Task storage (2 bytes) 18Bh-18Ch
X2TSK2 equ APS2Base+000Ch ;
AuxTstCm equ APS2Base+000Dh ; RAM:Auxlilary test command
MagKnPtr equ APS2Base+000Eh ; RAM:Logitech "Magic Knock" sequence pointer
RESMDEL equ APS2Base+000Fh ; RAM:init Resume delay
DLYCNTL equ APS2Base+0010h ; RAM:Delay timer low
DLYCNTH equ APS2Base+0011h ; RAM:Delay timer high
DLYPRSL equ APS2Base+0012h ; RAM:Delay timer prescaller low
DLYPRSH equ APS2Base+0013h ; RAM:Delay timer prescaller high
PCR0 equ APS2Base+014h ; previous CR0 value
; Reserved 9 bytes for customermization
CHRGFlshTm equ APS2Base+0020h ; RAM: Charging Status LED Flash Timer
THRMPolTm equ APS2Base+0021h ; RAM: Thermal Polling Timer
THRMNUM equ APS2Base+0022h ; RAM: # of SMB thermal sensors to be polled
THRMCTSK equ APS2Base+0023h ; RAM:Thermal Critical Task storage
THRMDLY equ APS2Base+0024h ; RAM:Thermal Polling Period
THRMFTSK equ APS2Base+0025h ; RAM:Thermal Polling Failure Task storage
; Reserved 10 bytes for customermization
SWQueStrt equ APS2Base+0030h ; SW Notification Queue start (10 bytes)
SWQueEnd equ APS2Base+003Ah ; SW Notification Queue end
SWTopPtr equ APS2Base+003Bh ; SWI Notification Queue Top pointer
SWBotPtr equ APS2Base+003Ch ; SWI Notification Queue Bottom ptr
SMBTSK equ APS2Base+003Dh ; RAM:SMbus Alarm Task
; equ APS2Base+003Eh ; RAM:
; equ APS2Base+003Fh ; RAM:
AK0DELTA equ APS2Base+0040h ; RAM:DAC/PWM 0 delta
AK0HIGH equ APS2Base+0041h ; RAM:DAC/PWM 0 High boundary
AK0LOW equ APS2Base+0042h ; RAM:DAC/PWM 0 Low boundary
AK1DELTA equ APS2Base+0043h ; RAM:DAC/PWM 1 delta
AK1HIGH equ APS2Base+0044h ; RAM:DAC/PWM 1 High boundary
AK1LOW equ APS2Base+0045h ; RAM:DAC/PWM 1 Low boundary
AK2DELTA equ APS2Base+0046h ; RAM:DAC/PWM 2 delta
AK2HIGH equ APS2Base+0047h ; RAM:DAC/PWM 2 High boundary
AK2LOW equ APS2Base+0048h ; RAM:DAC/PWM 2 Low boundary
AK3DELTA equ APS2Base+0049h ; RAM:DAC/PWM 3 delta
AK3HIGH equ APS2Base+004Ah ; RAM:DAC/PWM 3 High boundary
AK3LOW equ APS2Base+004Bh ; RAM:DAC/PWM 3 Low boundary
;---------------------- BATTERY SYSTEM SUPPORT VARIABLES --------------------
; Locations 280h-2BFh are shared (overlaid) by SBS
; variables. It is possible because only one type of Battery interface can
; active at a time.
;----------------------------------------------------------------------------
;------ SMBus and Smart Battery System (SBS) support variables.
RdBuffPtr equ 200h ; RAM: Read Cmd Buffer Pointer
SMBWtIdle equ 201h ; RAM: Wait for SMB Idle state time
SMBLowTime equ 202h ; RAM: 25ms for cumulative SMB Clk Low time
SMBLowTr equ 202h ; RAM: 25ms for cumulative SMB Clk Low time
SMBBuff equ 203h ; RAM: Read Cmd Data Buffer 203h-205h
FailDly equ 206h ; RAM: Polling Failure Period (must be <= 0Fh)
PolCmdCnt equ 207h ; RAM: Polling Command Counter
PolTimer equ 208h ; RAM: SMB Polling Timer
PollCmd0 equ 209h ; RAM: System defined Polling Command 0
StatReq equ 20Ah ; RAM: Battery Status Request
;PollCmd2 equ 20Bh ; RAM: System defined Polling Command 2
;PollCmd3 equ 20Ch ; RAM: System defined Polling Command 3
WrBuffPtr equ 20Dh ; RAM: Write Cmd Buffer Pointer
WrSMBBuff equ 20Eh ; RAM: Write Cmd Data Buffer 20Eh-20Fh
DataSMBBf equ WrSMBBuff+2 ; RAM: SMB Data Buffer 210h-230h
SBSCapab equ 231h ; RAM: SBS capabilities
SelPolStat equ 232h ; RAM: Selector Polling State 232h-233h
Bat0PolFlg equ 234h ; RAM: Battery 0 Polling Flags
;Bat1PolFlg equ 235h ; RAM: Battery 1 Polling Flags
;Bat2PolFlg equ 236h ; RAM: Battery 2 Polling Flags
;Bat3PolFlg equ 237h ; RAM: Battery 3 Polling Flags
SMBActTm equ 238h ; RAM: SMBus Activity Timer
TrnSMBTSK equ 239h ; RAM: Translated SMBus Alarm Task
AlertPin equ 23Ah ; RAM: SMBus Alert Pin virtual number
AlrtAdrPnd equ 23Bh ; RAM: SMBus Alert Pending Address
SMBMsgBf equ 23Ch ; RAM: SMBus Message Buffer 27Ch-27Eh
RecovTmr equ 23Fh ; RAM: SMBus Recovery Timer
Bat0PolRsp0 equ 240h ; RAM: Battery 0 Pol Cmnd 0 Respns 240h-241h
Bat0PolSta equ 242h ; RAM: Battery 0 Status Req Respns 242h-243h
;Bat0PolRsp2 equ 244h ; RAM: Battery 0 Pol Cmnd 2 Respns 244h-245h
;Bat0PolRsp3 equ 246h ; RAM: Battery 0 Pol Cmnd 3 Respns 246h-247h
;Bat1PolRsp equ 248h ; RAM: Battery 1 Pol Cmnd 0 Respns 248h-249h
;Bat1PolSta equ 24Ah ; RAM: Battery 1 Status Req Respns 24Ah-24Bh
;Bat1PolRsp2 equ 24Ch ; RAM: Battery 1 Pol Cmnd 2 Respns 24Ch-24Dh
;Bat1PolRsp3 equ 24Eh ; RAM: Battery 1 Pol Cmnd 3 Respns 24Eh-24Fh
;Bat2PolRsp equ 250h ; RAM: Battery 2 Pol Cmnd 0 Respns 250h-251h
;Bat2PolSta equ 252h ; RAM: Battery 2 Status Req Respns 252h-253h
;Bat2PolRsp2 equ 254h ; RAM: Battery 2 Pol Cmnd 2 Respns 254h-255h
;Bat2PolRsp3 equ 256h ; RAM: Battery 2 Pol Cmnd 3 Respns 256h-257h
;Bat3PolRsp equ 258h ; RAM: Battery 3 Pol Cmnd 0 Respns 258h-259h
;Bat3PolSta equ 25Ah ; RAM: Battery 3 Status Req Respns 25Ah-25Bh
;Bat3PolRsp2 equ 25Ch ; RAM: Battery 3 Pol Cmnd 2 Respns 25Ch-25Dh
;Bat3PolRsp3 equ 25Eh ; RAM: Battery 3 Pol Cmnd 2 Respns 25Eh-25Fh
Bat0Cmd0TP equ 260h ; RAM: Battery 0 Cmnd 0 Trip Point 260h-261h
;Bat1Cmd0TP equ 262h ; RAM: Battery 1 Cmnd 0 Trip Point 262h-263h
;Bat2Cmd0TP equ 264h ; RAM: Battery 2 Cmnd 0 Trip Point 264h-265h
;Bat3Cmd0TP equ 266h ; RAM: Battery 3 Cmnd 0 Trip Point 266h-267h
RdBuffPtr2 equ 280h ; RAM: Read Cmd Buffer Pointer
SMBWtIdle2 equ 281h ; RAM: Wait for SMB Idle state time
SMBLowTime2 equ 282h ; RAM: 25ms for cumulative SMB Clk Low time
SMBLowTr2 equ 282h ; RAM: 25ms for cumulative SMB Clk Low time
SMBBuff2 equ 283h ; RAM: Read Cmd Data Buffer 283h-285h
FailDly2 equ 286h ; RAM: Polling Failure Period (must be <= 0Fh)
PolCmdCnt2 equ 287h ; RAM: Polling Command Counter
PolTimer2 equ 288h ; RAM: SMB Polling Timer
PollCmd02 equ 289h ; RAM: System defined Polling Command 0
StatReq2 equ 28Ah ; RAM: Battery Status Request
;PollCmd22 equ 28Bh ; RAM: System defined Polling Command 2
;PollCmd32 equ 28Ch ; RAM: System defined Polling Command 3
WrBuffPtr2 equ 28Dh ; RAM: Write Cmd Buffer Pointer
WrSMBBuff2 equ 28Eh ; RAM: Write Cmd Data Buffer 28Eh-28Fh
DataSMBBf2 equ WrSMBBuff2+2; RAM: SMB Data Buffer 290h-2C0h
RecovTmr2 equ 2B1h ; RAM: SMBus 2 Recovery Timer
SMBActTm2 equ 2B2h ; RAM: SMBus Activity Timer
;---------------------- ACPI EC SUPPORT VARIABLES ---------------------------
ECSpace equ 300h ; Start of EC address space
ECTMO equ ECSpace+00h ; EC Total Burst Time RAM:2C0h
SCICTRL equ ECSpace+01h ; SCI control byte RAM:2C1h
SCIPULSE equ ECSpace+02h ; SCI Pulse size RAM:2C2h
CMCmd equ ECSpace+04h ; Control Methods Command Register
CMDat1 equ ECSpace+05h ; Control Methods Data 1 Register
CMDat2 equ ECSpace+06h ; Control Methods Data 2 Register
CMDat3 equ ECSpace+07h ; Control Methods Data 3 Register
ECRETVCT equ ECSpace+08h ; EC Data Return Vector storage (2 bytes)
ECQueStrt equ ECSpace+0Ah ; EC Notification Queue start (8 bytes)
ECQueEnd equ ECSpace+12h ; EC Notification Queue end
ECTopPtr equ ECSpace+12h ; EC Notification Queue Top pointer
ECBotPtr equ ECSpace+14h ; EC Notification Queue Bottom ptr
ECAdrTmp equ ECSpace+17h ; EC Address Temporary storage
;------ SMBus Host Registers
ECSMBBase equ ECSpace+18h ; EC SMBus Registers Base RAM:2D8h-2FCh
SMB_PRTC equ ECSMBBase+00h ; EC SMBus Protocol Register
SMB_STS equ ECSMBBase+01h ; EC SMBus Status Register
SMB_ADDR equ ECSMBBase+02h ; EC SMBus Address Register
SMB_CMD equ ECSMBBase+03h ; EC SMBus Command Register
SMB_DATA equ ECSMBBase+04h ; EC SMBus Data Register array (32 b)
SMB_BCNT equ ECSMBBase+24h ; EC SMBus Block Count Register
; SBS Only Alarm Registers RAM:2FDh-2FFh
SMB_ALRA equ ECSMBBase+25h ; EC SMBus Alarm Address Register
SMB_ALRD0 equ ECSMBBase+26h ; EC SMBus Alarm Data Register 0
SMB_ALRD1 equ ECSMBBase+27h ; EC SMBus Alarm Data Register 1
; Non SBS Alarm Registers RAM:300h-302h
SMB2ALRA equ ECSMBBase+28h ; EC SMBus Alarm 2 Address Register
SMB2ALRD0 equ ECSMBBase+29h ; EC SMBus Alarm 2 Data Register 0
SMB2ALRD1 equ ECSMBBase+2Ah ; EC SMBus Alarm 2 Data Register 1
;------ SMBus 2 Host Registers
ECSMB2Base equ ECSpace+40h ; EC SMBus Registers Base RAM:300h-32Ah
SMB2_PRTC equ ECSMB2Base+00h ; EC SMBus 2 Protocol Register
SMB2_STS equ ECSMB2Base+01h ; EC SMBus 2 Status Register
SMB2_ADDR equ ECSMB2Base+02h ; EC SMBus 2 Address Register
SMB2_CMD equ ECSMB2Base+03h ; EC SMBus 2 Command Register
SMB2_DATA equ ECSMB2Base+04h ; EC SMBus 2 Data Register array (32 b)
SMB2_BCNT equ ECSMB2Base+24h ; EC SMBus 2 Block Count Register
; SBS Only Alarm Registers RAM:325h-327h
SMB2_ALRA equ ECSMB2Base+25h ; EC SMBus 2 Alarm Address Register
SMB2_ALRD0 equ ECSMB2Base+26h ; EC SMBus 2 Alarm Data Register 0
SMB2_ALRD1 equ ECSMB2Base+27h ; EC SMBus 2 Alarm Data Register 1
; Non SBS Alarm Registers RAM:328h-32Ah
SMB22ALRA equ ECSMB2Base+28h ; EC SMBus 2 Alarm 2 Address Register
SMB22ALRD0 equ ECSMB2Base+29h ; EC SMBus 2 Alarm 2 Data Register 0
SMB22ALRD1 equ ECSMB2Base+2Ah ; EC SMBus 2 Alarm 2 Data Register 1
;------ Input Pin Monitoring
Slp_Typ equ ECSpace+07Fh ; System Sleep Type storage RAM:37Fh
NmWKI equ 004h ; 2 Wake Inputs: P5.4,P5.5
;WKISTATE equ ECSpace+43h ; WKI debouncd state RAM:303h
;WKIDEBTM equ ECSpace+44h ; WKI debounce tmers RAM:304h-307h
;WKISPEC equ ECSpace+48h ; WKI specifications RAM:308h-30Bh
;P54SPEC equ WKISPEC+0 ; P5.4 specification
;WKITASK equ ECSpace+4Ch ; WKI event tasks RAM:30Ch-30Fh
NmPXEI equ 008h ; 8 Event Inputs PX.Y-Z
PXYSPEC equ ECSpace+080h ; PX.Y-Z pin specifications RAM:380h-3XXh
PXYTASK equ PXYSPEC+NmPXEI*1; PX.Y-Z pin event tasks RAM:
PXYLOW equ PXYSPEC+NmPXEI*2; PX.Y-Z signal low limits RAM:
PXYHIGH equ PXYSPEC+NmPXEI*3; PX.Y-Z signal high limits RAM:
PXYVALUE equ PXYSPEC+NmPXEI*4; PX.Y-Z signal value RAM:
PXYSTATE equ PXYSPEC+NmPXEI*5 ; PX.Y-Z debounced pin sate RAM:
PXYSTATE1 equ PXYSTATE+1 ; PX.Y-Z debounced pin sate RAM:
StpRpFLG equ PXYSTATE+2 ; PX.Y-Z pin stop rpt flags RAM:
StpRpFLG1 equ PXYSTATE+3 ; PX.Y-Z pin stop rpt flags RAM:
HystFLG equ PXYSTATE+4 ; PX.Y-Z pin Hyst rpt flags RAM:
HystFLG1 equ PXYSTATE+5 ; PX.Y-Z pin Hyst rpt flags RAM:
;------ Thermal Sen⌨️ 快捷键说明
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