📄 rcf_dsp48.xco
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# BEGIN Project OptionsSET flowvendor = Foundation_iSESET vhdlsim = TrueSET verilogsim = TrueSET workingdirectory = D:\work\ISE\c7SET speedgrade = -12SET simulationfiles = BehavioralSET asysymbol = TrueSET addpads = FalseSET device = xc4vsx35SET implementationfiletype = EdifSET busformat = BusFormatAngleBracketNotRippedSET foundationsym = FalseSET package = ff668SET createndf = FalseSET designentry = VHDLSET devicefamily = virtex4SET formalverification = FalseSET removerpms = False# END Project Options# BEGIN SelectSELECT Multiply_Accumulator family Xilinx,_Inc. 4.0# END Select# BEGIN ParametersCSET b_width=16CSET a_width=16CSET mac_count=16CSET clock_frequency=61.44CSET has_reset=falseCSET has_mult_pipeline_register=trueCSET has_mult_output_register=falseCSET has_clock_enable=falseCSET a_type=SignedCSET component_name=rcf_dsp48CSET use_embedded_mult=EmbeddedCSET round_operation=ConvergentCSET has_output_register=falseCSET b_type=SignedCSET result_width=36CSET has_mult_input_register=falseCSET auto_pipeline=trueCSET enable_rlocs=false# END ParametersGENERATE
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