spi_master.txt

This is a verilog code used oversampled clock to implement SPI slave. Also include C code for a ARM

void main(void)
{
  // initialize SSP
  SSP0CPSR = 0x02;  // SSP max speed
  SSP0CR0 = 0x07;  // SSP max speed, 8 bits
  SSP0CR1 = 0x02;  // SSP master mode
  PINSEL1 = 0x2A8;  // SSP mode for pins P0.17 to P0.20

  while(1)
  {
    // send two bytes
    SSP0DR = 0x55;  // one nice thing about the SSP is that it has a 8-words deep FIFO
    SSP0DR = 0x54;  // so here we write the data to be sent without worrying

    // now wait until both bytes are sent
    while(!(SSP0SR & 0x01));

    // now we can read the two bytes received... and do anything with them
    int data1 = SSP0DR;
    int data2 = SSP0DR;
    // ...
  }
}