📄 dts_drv.c
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/*C**************************************************************************
* NAME: dts_drv.c
*----------------------------------------------------------------------------
* Copyright (c) 2006 Atmel.
*----------------------------------------------------------------------------
* RELEASE: C51 Sample
* REVISION: 1.00
*----------------------------------------------------------------------------
*
*****************************************************************************/
#include "system\reg51.h"
#include "system\compiler.h"
#include "driver\dts_drv.h" /* scheduler definition */
#include "driver\io_def.h"
/*F**************************************************************************
* NAME: dts_In1mode
*----------------------------------------------------------------------------
* PARAMS:
* dts_In1mode
* return:
*----------------------------------------------------------------------------
* PURPOSE:
*----------------------------------------------------------------------------
* EXAMPLE:
*----------------------------------------------------------------------------
* NOTE:
*----------------------------------------------------------------------------
* REQUIREMENTS:
*****************************************************************************/
/*
void radio_init()
{
Byte i;
for (i=0;i<6;i++)
{
WriteData[i]=0;
}
if(Band ==RADIO_BAND_FM)
{
// 8bit :(H)SNS DVS CTE XS RO R1 R2 R3(L)
// bit :(H) R3 R2 R1 R0 XS CTE DVS SNS (L) ZHUQIAO
// 0001 $ 0010b
WriteData[2] = 0x12; //0001=>ref=50//0011=>ref=25 FM: SNS DVS :* 1;COUNTER RESET: CTE=0; 4.5MHZ XS=0; PLL_FREQ 50KHZ R0R1R2R3=1100;
//(H)IOC1 IOC2 IO1 IO2 BO1 BO2 BO3 BO4(L)
// (H) BO4 BO3 BO2 BO1 IO2 IO1 IOC2 IOC1 (L)
// 1010 $ 0011b
WriteData[3] = 0xa3;
//(H)BO5 DOC0 DOC1 DOC2 UL0 UL1 DZ0 DZ1(L)
// (H) DZ1 DZ0 UL1 UL0 DOC2 DOC1 DOC0 BO5 (L)
// 1111 $ 0100b
WriteData[4] = 0xf4;
//(H)GT0 GT1 TBC DLC IFS TEST0 TEST1 TEST2(L)
// (H) TEST2 TEST1 TEST0 IFS DLC TBC GT1 GT0 (L)
// 0001 $ 0000b
WriteData[5] = 0x10; //GT=4ms
}
else
if(Band ==RADIO_BAND_AM)
{
// bit :(H) R3 R2 R1 R0 XS CTE DVS SNS (L) ZHUQIAO
// 1000 $ 0000b
WriteData[2] = AM_WRITE_2; //0x80 ref=10khz//0x90 ref=9k wM: SNS DVS :00;COUNTER RESET: CTE=0; 4.5MHZ XS=0; PLL_FREQ=10KHZ R0R1R2R3=0001;
// (H) BO4 BO3 BO2 BO1 IO2 IO1 IOC2 IOC1 (L)
// 1001 $ 0011b
WriteData[3] = 0x93;
// (H) DZ1 DZ0 UL1 UL0 DOC2 DOC1 DOC0 BO5 (L)
// 1111 $ 0100b
WriteData[4] = 0xf4;
// (H) TEST2 TEST1 TEST0 IFS DLC TBC GT1 GT0 (L)
// 0001 $ 0000b
WriteData[5] = 0x10; //GT=4ms
}
}
*/
void dts_In1mode (void)
{
DTS_CE = 0;
getByteLSB(0x28);
DTS_CE = 1;
getByteLSB(DTS_buffer[0]);
getByteLSB(DTS_buffer[1]);
getByteLSB(DTS_buffer[2]);
DTS_CE = 0;
}
/*F**************************************************************************
* NAME: dts_In2mode
*----------------------------------------------------------------------------
* PARAMS:
* dts_In1mode
* return:
*----------------------------------------------------------------------------
* PURPOSE:
*----------------------------------------------------------------------------
* EXAMPLE:
*----------------------------------------------------------------------------
* NOTE:
*----------------------------------------------------------------------------
* REQUIREMENTS:
*****************************************************************************/
void dts_In2mode (void)
{
DTS_CE = 0;
getByteLSB(0x29);
DTS_CE = 1;
getByteLSB(DTS_buffer[3]);
getByteLSB(DTS_buffer[4]);
getByteLSB(DTS_buffer[5]);
DTS_CE = 0;
}
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