lpc2300.mod

oberon 07 clock for lpc23xx NXP (Philips) chip

T3CTCr* = 0E0074070H;


(* Pulse Width Modulator (Pwm) *)
Pwm0BaseAddr*= 0E0014000H;
Pwm0IR* = 0E0014000H;
Pwm0TCr* = 0E0014004H;
Pwm0TC* = 0E0014008H;
Pwm0PR* = 0E001400CH;
Pwm0PC* = 0E0014010H;
Pwm0MCr* = 0E0014014H;
Pwm0MR0* = 0E0014018H;
Pwm0MR1* = 0E001401CH;
Pwm0MR2* = 0E0014020H;
Pwm0MR3* = 0E0014024H;
Pwm0CCr* = 0E0014028H;
Pwm0Cr0* = 0E001402CH;
Pwm0Cr1* = 0E0014030H;
Pwm0Cr2* = 0E0014034H;
Pwm0Cr3* = 0E0014038H;
Pwm0EMR* = 0E001403CH;
Pwm0MR4* = 0E0014040H;
Pwm0MR5* = 0E0014044H;
Pwm0MR6* = 0E0014048H;
Pwm0PCr* = 0E001404CH;
Pwm0LER* = 0E0014050H;
Pwm0CTCr* = 0E0014070H;

Pwm1BaseAddr* = 0E0018000H;
Pwm1IR* = 0E0018000H;
Pwm1TCr* = 0E0018004H;
Pwm1TC* = 0E0018008H;
Pwm1PR* = 0E001800CH;
Pwm1PC* = 0E0018010H;
Pwm1MCr* = 0E0018014H;
Pwm1MR0* = 0E0018018H;
Pwm1MR1* = 0E001801CH;
Pwm1MR2* = 0E0018020H;
Pwm1MR3* = 0E0018024H;
Pwm1CCr* = 0E0018028H;
Pwm1Cr0* = 0E001802CH;
Pwm1Cr1* = 0E0018030H;
Pwm1Cr2* = 0E0018034H;
Pwm1Cr3* = 0E0018038H;
Pwm1EMR* = 0E001803CH;
Pwm1MR4* = 0E0018040H;
Pwm1MR5* = 0E0018044H;
Pwm1MR6* = 0E0018048H;
Pwm1PCr* = 0E001804CH;
Pwm1LER* = 0E0018050H;
Pwm1CTCr* = 0E0018070H;


(* Universal Asynchronous Receiver Transmitter 0 (UART0) *)
UART0BaseAddr* = 0E000C000H;
U0RBR* = 0E000C000H;
U0THR* = 0E000C000H;
U0DLL* = 0E000C000H;
U0DLM* = 0E000C004H;
U0IER* = 0E000C004H;
U0IIR* = 0E000C008H;
U0FCr* = 0E000C008H;
U0LCr* = 0E000C00CH;
U0LSR* = 0E000C014H;
U0SCr* = 0E000C01CH;
U0ACr* = 0E000C020H;
U0ICr* = 0E000C024H;
U0FDR* = 0E000C028H;
U0TER* = 0E000C030H;

(* Universal Asynchronous Receiver Transmitter 1 (UART1) *)
UART1BaseAddr* = 0E0010000H;
U1RBR* = 0E0010000H;
U1THR* = 0E0010000H;
U1DLL* = 0E0010000H;
U1DLM* = 0E0010004H;
U1IER* = 0E0010004H;
U1IIR* = 0E0010008H;
U1FCr* = 0E0010008H;
U1LCr* = 0E001000CH;
U1MCr* = 0E0010010H;
U1LSR* = 0E0010014H;
U1MSR* = 0E0010018H;
U1SCr* = 0E001001CH;
U1ACr* = 0E0010020H;
U1FDR* = 0E0010028H;
U1TER* = 0E0010030H;

(* Universal Asynchronous Receiver Transmitter 2 (UART2) *)
UART2BaseAddr* = 0E0078000H;
U2RBR* = 0E0078000H;
U2THR* = 0E0078000H;
U2DLL* = 0E0078000H;
U2DLM* = 0E0078004H;
U2IER* = 0E0078004H;
U2IIR* = 0E0078008H;
U2FCr* = 0E0078008H;
U2LCr* = 0E007800CH;
U2LSR* = 0E0078014H;
U2SCr* = 0E007801CH;
U2ACr* = 0E0078020H;
U2ICr* = 0E0078024H;
U2FDR* = 0E0078028H;
U2TER* = 0E0078030H;

(* Universal Asynchronous Receiver Transmitter 3 (UART3) *)
UART3BaseAddr* = 0E007C000H;
U3RBR* = 0E007C000H;
U3THR* = 0E007C000H;
U3DLL* = 0E007C000H;
U3DLM* = 0E007C004H;
U3IER* = 0E007C004H;
U3IIR* = 0E007C008H;
U3FCr* = 0E007C008H;
U3LCr* = 0E007C00CH;
U3LSR* = 0E007C014H;
U3SCr* = 0E007C01CH;
U3ACr* = 0E007C020H;
U3ICr* = 0E007C024H;
U3FDR* = 0E007C028H;
U3TER* = 0E007C030H;

(* I2C Interface 0 *)
I2C0BaseAddr* = 0E001C000H;
I20ConSet* = 0E001C000H;
I20Stat* = 0E001C004H;
I20DAT* = 0E001C008H;
I20ADR* = 0E001C00CH;
I20SCLH* = 0E001C010H;
I20SCLL* = 0E001C014H;
I20ConClr* = 0E001C018H;

(* I2C Interface 1 *)
I2C1BaseAddr* = 0E005C000H;
I21ConSet* = 0E005C000H;
I21Stat* = 0E005C004H;
I21DAT* = 0E005C008H;
I21ADR* = 0E005C00CH;
I21SCLH* = 0E005C010H;
I21SCLL* = 0E005C014H;
I21ConClr* = 0E005C018H;

(* I2C Interface 2 *)
I2C2BaseAddr* = 0E0080000H;
I22ConSet* = 0E0080000H;
I22Stat* = 0E0080004H;
I22DAT* = 0E0080008H;
I22ADR* = 0E008000CH;
I22SCLH* = 0E0080010H;
I22SCLL* = 0E0080014H;
I22ConClr* = 0E0080018H;

(* SPI0 (Serial Peripheral Interface 0) *)
SPI0BaseAddr* = 0E0020000H;
S0SPCr* = 0E0020000H;
S0SPSR* = 0E0020004H;
S0SPDR* = 0E0020008H;
S0SPCCr* = 0E002000CH;
S0SPInt* = 0E002001CH;

(* Ssp0 Controller *)
Ssp0BaseAddr* = 0E0068000H;
Ssp0Cr0* = 0E0068000H;
Ssp0Cr1* = 0E0068004H;
Ssp0DR* = 0E0068008H;
Ssp0SR* = 0E006800CH;
Ssp0CPSR* = 0E0068010H;
Ssp0IMSC* = 0E0068014H;
Ssp0RIS* = 0E0068018H;
Ssp0MIS* = 0E006801CH;
Ssp0ICr* = 0E0068020H;
Ssp0DMacr* = 0E0068024H;

(* Ssp1 Controller *)
Ssp1BaseAddr* = 0E0030000H;
Ssp1Cr0* = 0E0030000H;
Ssp1Cr1* = 0E0030004H;
Ssp1DR* = 0E0030008H;
Ssp1SR* = 0E003000CH;
Ssp1CPSR* = 0E0030010H;
Ssp1IMSC* = 0E0030014H;
Ssp1RIS* = 0E0030018H;
Ssp1MIS* = 0E003001CH;
Ssp1ICr* = 0E0030020H;
Ssp1DMacr* = 0E0030024H;


(* Real Time Clock *)
RtcBaseAddr* = 0E0024000H;
RtcILR* = 0E0024000H;
RtcCTC* = 0E0024004H;
RtcCCr* = 0E0024008H;
RtcCIIR* = 0E002400CH;
RtcAMR* = 0E0024010H;
RtcCTimE0* = 0E0024014H;
RtcCTimE1* = 0E0024018H;
RtcCTimE2* = 0E002401CH;
RtcSEC* = 0E0024020H;
RtcMIN* = 0E0024024H;
RtcHOUR* = 0E0024028H;
RtcDOM* = 0E002402CH;
RtcDOW* = 0E0024030H;
RtcDOY* = 0E0024034H;
RtcMONTH* = 0E0024038H;
RtcYEAR* = 0E002403CH;
RtcCISS* = 0E0024040H;
RtcALSEC* = 0E0024060H;
RtcALMIN* = 0E0024064H;
RtcALHOUR* = 0E0024068H;
RtcALDOM* = 0E002406CH;
RtcALDOW* = 0E0024070H;
RtcALDOY* = 0E0024074H;
RtcALMON* = 0E0024078H;
RtcALYEAR* = 0E002407CH;
RtcPREInt* = 0E0024080H;
RtcPREFRAC* = 0E0024084H;


(* A/D Converter 0 (AD0) *)
AD0BaseAddr* = 0E0034000H;
AD0Cr* = 0E0034000H;
AD0GDR* = 0E0034004H;
AD0IntEn* = 0E003400CH;
AD0DR0* = 0E0034010H;
AD0DR1* = 0E0034014H;
AD0DR2* = 0E0034018H;
AD0DR3* = 0E003401CH;
AD0DR4* = 0E0034020H;
AD0DR5* = 0E0034024H;
AD0DR6* = 0E0034028H;
AD0DR7* = 0E003402CH;
AD0Stat* = 0E0034030H;


(* D/A Converter *)
DACBaseAddr* = 0E006C000H;
DACr* = 0E006C000H;


(* Watchdog *)
WDGBaseAddr* = 0E0000000H;
WDMOD* = 0E0000000H;
WDTC* = 0E0000004H;
WDFeed* = 0E0000008H;
WDTV* = 0E000000CH;
WDClkSel* = 0E0000010H;

(* Can ControlLERS AND ACCEPTANCE Filter *)
CanACCEPTBaseAddr* = 0E003C000H;
CanAFMR* = 0E003C000H;  	
CanSFFSA* = 0E003C004H;  	
CanSFFGRPSA* = 0E003C008H;
CanEFFSA* = 0E003C00CH;
CanEFFGRPSA* = 0E003C010H;  	
CanEOT* = 0E003C014H;
CanLUTERRADR* = 0E003C018H;  	
CanLUTERR* = 0E003C01CH;

CanCEnTRALBaseAddr* = 0E0040000H;  	
CanTXSR* = 0E0040000H;  	
CanRXSR* = 0E0040004H;  	
CanMSR* = 0E0040008H;

Can1BaseAddr* = 0E0044000H;
Can1MOD* = 0E0044000H;  	
Can1CMR* = 0E0044004H;  	
Can1GSR* = 0E0044008H;  	
Can1ICr* = 0E004400CH;  	
Can1IER* = 0E0044010H;
Can1BTR* = 0E0044014H;  	
Can1EWL* = 0E0044018H;  	
Can1SR* = 0E004401CH;  	
Can1RFS* = 0E0044020H;  	
Can1RID* = 0E0044024H;
Can1RDA* = 0E0044028H;  	
Can1RDB* = 0E004402CH;
  	
Can1TFI1* = 0E0044030H;  	
Can1TID1* = 0E0044034H;  	
Can1TDA1* = 0E0044038H;
Can1TDB1* = 0E004403CH;  	
Can1TFI2* = 0E0044040H;  	
Can1TID2* = 0E0044044H;  	
Can1TDA2* = 0E0044048H;  	
Can1TDB2* = 0E004404CH;
Can1TFI3* = 0E0044050H;  	
Can1TID3* = 0E0044054H;  	
Can1TDA3* = 0E0044058H;  	
Can1TDB3* = 0E004405CH;

Can2BaseAddr* = 0E0048000H;
Can2MOD* = 0E0048000H;  	
Can2CMR* = 0E0048004H;  	
Can2GSR* = 0E0048008H;  	
Can2ICr* = 0E004800CH;  	
Can2IER* = 0E0048010H;
Can2BTR* = 0E0048014H;  	
Can2EWL* = 0E0048018H;  	
Can2SR* = 0E004801CH;  	
Can2RFS* = 0E0048020H;  	
Can2RID* = 0E0048024H;
Can2RDA* = 0E0048028H;  	
Can2RDB* = 0E004802CH;
  	
Can2TFI1* = 0E0048030H;  	
Can2TID1* = 0E0048034H;  	
Can2TDA1* = 0E0048038H;
Can2TDB1* = 0E004803CH;  	
Can2TFI2* = 0E0048040H;  	
Can2TID2* = 0E0048044H;  	
Can2TDA2* = 0E0048048H;  	
Can2TDB2* = 0E004804CH;
Can2TFI3* = 0E0048050H;  	
Can2TID3* = 0E0048054H;  	
Can2TDA3* = 0E0048058H;  	
Can2TDB3* = 0E004805CH;


(* MulTimedia Card Interface(Mci) Controller *)
MciBaseAddr* = 0E008C000H;
MciPOWER* = 0E0048000H;
MciCLOCK* = 0E0048004H;
MciARGUMEnT* = 0E0048008H;
MciCommand* = 0E004800CH;
MciRESPCMD* = 0E0048010H;
MciRESP0* = 0E0048014H;
MciRESP1* = 0E0048018H;
MciRESP2* = 0E004801CH;
MciRESP3* = 0E0048020H;
MciDATATMR* = 0E0048024H;
MciDATALEn* = 0E0048028H;
MciDATACtrl* = 0E004802CH;
MciDATACnt* = 0E0048030H;
MciStatus* = 0E0048034H;
MciClear* = 0E0048038H;
MciMask0* = 0E004803CH;
MciMask1* = 0E0048040H;
MciFIFOCnt* = 0E0048048H;
MciFIFO* = 0E0048080H;


(* I2S Interface Controller (I2S) *)
I2SBaseAddr* = 0E0088000H;
I2SDAO* = 0E0088000H;
I2SDAI* = 0E0088004H;
I2STXFIFO* = 0E0088008H;
I2SRXFIFO* = 0E008800CH;
I2SStatE* = 0E0088010H;
I2SDMA1* = 0E0088014H;
I2SDMA2* = 0E0088018H;
I2SIrq* = 0E008801CH;
I2STXRATE* = 0E0088020H;
I2SRXRATE* = 0E0088024H;


(* GEneral-purpose DMA Controller *)
DMABaseAddr* = 0FFE04000H;
GPDMAIntStat* = 0FFE04000H;
GPDMAIntTCStat* = 0FFE04004H;
GPDMAIntTCClr* = 0FFE04008H;
GPDMAIntERRStat* = 0FFE0400CH;
GPDMAIntERRClr* = 0FFE04010H;
GPDMARAWIntTCStat* = 0FFE04014H;
GPDMARAWIntERRStat* = 0FFE04018H;
GPDMAEnableDCHNS* = 0FFE0401CH;
GPDMASOFTBREQ* = 0FFE04020H;
GPDMASOFTSREQ* = 0FFE04024H;
GPDMASOFTLBREQ* = 0FFE04028H;
GPDMASOFTLSREQ* = 0FFE0402CH;
GPDMaConfig* = 0FFE04030H;
GPDMASYNC* = 0FFE04034H;

(* DMA channel 0 registers *)
GPDMacH0SRC* = 0FFE04100H;
GPDMacH0DEST* = 0FFE04104H;
GPDMacH0LLI* = 0FFE04108H;
GPDMacH0Ctrl* = 0FFE0410CH;
GPDMacH0Cfg* = 0FFE04110H;

(* DMA channel 1 registers *)
GPDMacH1SRC* = 0FFE04120H;
GPDMacH1DEST* = 0FFE04124H;
GPDMacH1LLI* = 0FFE04128H;
GPDMacH1Ctrl* = 0FFE0412CH;
GPDMacH1Cfg* = 0FFE04130H;


(* Usb Controller *)
UsbIntBaseAddr* = 0E01FC1C0H;
UsbBaseAddr* = 0FFE0C200H;		(* Usb Base Address *)

UsbIntStat* = 0E01FC1C0H;

(* Usb DeVice Interrupt Registers *)
DEVIntStat* = 0FFE0C200H;
DEVIntEn* = 0FFE0C204H;
DEVIntClr* = 0FFE0C208H;
DEVIntSet* = 0FFE0C20CH;
DEVIntPRIo* = 0FFE0C22CH;

(* Usb DeVice EndpoInt Interrupt Registers *)
EPIntStat* = 0FFE0C230H;
EPIntEn* = 0FFE0C234H;
EPIntClr* = 0FFE0C238H;
EPIntSet* = 0FFE0C23CH;
EPIntPRIo* = 0FFE0C240H;

(* Usb DeVice EndpoInt RealizatIon Registers *)
REALIZEEP* = 0FFE0C244H;
EPIndex* = 0FFE0C248H;
MAXPACKETSIZE* = 0FFE0C24CH;

(* Usb DeVice Command Reagisters *)
CMDCODE* = 0FFE0C210H;
CMDDATA* = 0FFE0C214H;

(* Usb DeVice Data Transfer Registers *)
RXDATA* = 0FFE0C218H;
TXDATA* = 0FFE0C21CH;
RXPLEnGTH* = 0FFE0C220H;
TXPLEnGTH* = 0FFE0C224H;
UsbCtrl* = 0FFE0C228H;

(* Usb DeVice DMA Registers *)
DMAREQStat* = 0FFE0C250H;
DMAREQClr* = 0FFE0C254H;
DMAREQSet* = 0FFE0C258H;
UDCAHEAD* = 0FFE0C280H;
EPDMAStat* = 0FFE0C284H;
EPDMAEn* = 0FFE0C288H;
EPDMADIS* = 0FFE0C28CH;
DMAIntStat* = 0FFE0C290H;
DMAIntEn* = 0FFE0C294H;
EOTIntStat* = 0FFE0C2A0H;
EOTIntClr* = 0FFE0C2A4H;
EOTIntSet* = 0FFE0C2A8H;
NDDREQIntStat* = 0FFE0C2ACH;
NDDREQIntClr* = 0FFE0C2B0H;
NDDREQIntSet* = 0FFE0C2B4H;
SYSERRIntStat* = 0FFE0C2B8H;
SYSERRIntClr* = 0FFE0C2BCH;
SYSERRIntSet* = 0FFE0C2C0H;

(* Usb Host and Otg registers are for LPC24xx only *)
(* Usb Host Controller *)
UsbHcBaseAddr* = 0FFE0C000H;
HcRevision* = 0FFE0C000H;
HcControl* = 0FFE0C004H;
HcCMDStat* = 0FFE0C008H;
HcIntStat* = 0FFE0C00CH;
HcIntEn* = 0FFE0C010H;
HcIntDIS* = 0FFE0C014H;
HcHcCA* = 0FFE0C018H;
HcPERIoDCURED* = 0FFE0C01CH;
HcCtrlHEADED* = 0FFE0C020H;
HcCtrlCURED* = 0FFE0C024H;
HcBULKHEADED* = 0FFE0C028H;
HcBULKCURED* = 0FFE0C02CH;
HcDONEHEAD* = 0FFE0C030H;
HcFMIntERVAL* = 0FFE0C034H;
HcFMREMAINING* = 0FFE0C038H;
HcFMNumBER* = 0FFE0C03CH;
HcPERIoDStaRT* = 0FFE0C040H;
HcLSTHRHLD* = 0FFE0C044H;
HcRHDESCA* = 0FFE0C048H;
HcRHDESCB* = 0FFE0C04CH;
HcRHStat* = 0FFE0C050H;
HcRHPortStat1* = 0FFE0C054H;
HcRHPortStat2* = 0FFE0C058H;

(* Usb Otg Controller *)
UsbOtgBaseAddr* = 0FFE0C100H;
OtgIntStat* = 0FFE0C100H;
OtgIntEn* = 0FFE0C104H;
OtgIntSet* = 0FFE0C108H;
OtgIntClr* = 0FFE0C10CH;
(* On LPC23xx, the name is UsbPortSel, on LPC24xx, the name is OtgStatCtrl 
UsbPortSel* = 0FFE0C110H;*)
OtgTimER* = 0FFE0C114H;

UsbOtgI2CBaseAddr* =	0FFE0C300H;
OtgI2CRX* = 0FFE0C300H;
OtgI2CTX* = 0FFE0C300H;
OtgI2CSts* = 0FFE0C304H;
OtgI2CCtl* = 0FFE0C308H;
OtgI2CClkHI* = 0FFE0C30CH;
OtgI2CClkLO* = 0FFE0C310H;

(* On LPC23xx, the names are UsbClkCtrl and UsbClkSt; on LPC24xx, the names are 
OtgClkCtrl and OtgClkStat respectively. *)
UsbOtgClkBaseAddr* =	0FFE0CFF0H;
(*UsbClkCtrl* = 0FFE0CF04H;
UsbClkSt* = 0FFE0CF08H;*)

(* Note: below three register name ConvEntIon is for LPC23xx Usb deVice only, match with the spec. update in Usb DeVice SectIon. *) 
UsbPortSel* = 0FFE0C110H;
UsbClkCtrl* = 0FFE0CF04H;
UsbClkSt* = 0FFE0CF08H;

(* Ethernet Mac (32 bit data bus) -- all registers are RW unless indicated in parEntheses *)
MacBaseAddr* = 0FFE00000H; (* Ahb Peripheral # 0 *)
MacMac1* = 0FFE00000H; (* Mac Config reg 1 *)
MacMac2* = 0FFE00004H; (* Mac Config reg 2 *)
MacIPGT* = 0FFE00008H; (* b2b InterPacketGap reg *)
MacIPGR* = 0FFE0000CH; (* non b2b InterPacketGap reg *)
MacClrT* = 0FFE00010H; (* CoLlisIon window/ReTry reg *)
MacMAXF* = 0FFE00014H; (* MAXimum Frame reg *)
MacSUPP* = 0FFE00018H; (* PHY SUPPort reg *)
MacTEST* = 0FFE0001CH; (* TEST reg *)
MacMCfg* = 0FFE00020H; (* MII Mgmt Config reg *)
MacMCMD* = 0FFE00024H; (* MII Mgmt Command reg *)
MacMADR* = 0FFE00028H; (* MII Mgmt Address reg *)
MacMWTD* = 0FFE0002CH; (* MII Mgmt WriTe Data reg (WO) *)
MacMRDD* = 0FFE00030H; (* MII Mgmt ReaD Data reg (RO) *)
MacMIND* = 0FFE00034H; (* MII Mgmt INDicators reg (RO) *)

MacSA0* = 0FFE00040H; (* StatIon Address 0 reg *)
MacSA1* = 0FFE00044H; (* StatIon Address 1 reg *)
MacSA2* = 0FFE00048H; (* StatIon Address 2 reg *)

MacCommand* = 0FFE00100H; (* Command reg *)
MacStatus* = 0FFE00104H; (* Status reg (RO) *)
MacRXDescriptor* = 0FFE00108H; (* Rx Descriptor Base Address reg *)
MacRXStatus* = 0FFE0010CH; (* Rx Status Base Address reg *)
MacRXDescriptorNum* = 0FFE00110H; (* Rx Number of Descriptors reg *)
MacRXProduceIndex* = 0FFE00114H; (* Rx Produce Index reg (RO) *)
MacRXConsumeIndex* = 0FFE00118H; (* Rx Consume Index reg *)
MacTXDescriptor* = 0FFE0011CH; (* Tx Descriptor Base Address reg *)
MacTXStatus* = 0FFE00120H; (* Tx Status Base Address reg *)
MacTXDescriptorNum* = 0FFE00124H; (* Tx Number of Descriptors reg *)
MacTXProduceIndex* = 0FFE00128H; (* Tx Produce Index reg *)
MacTXConsumeIndex* = 0FFE0012CH; (* Tx Consume Index reg (RO) *)

MacTSV0* = 0FFE00158H; (* Tx Status vector 0 reg (RO) *)
MacTSV1* = 0FFE0015CH; (* Tx Status vector 1 reg (RO) *)
MacRSV* =  0FFE00160H; (* Rx Status vector reg (RO) *)

MacFlowControlCnt* = 0FFE00170H; (* Flow Control counter reg *)
MacFlowControlSts* = 0FFE00174H; (* Flow Control Status reg *)

MacRXFilterCtrl* = 0FFE00200H; (* Rx Filter Ctrl reg *)
MacRXFilterWOLSts* = 0FFE00204H; (* Rx Filter WoL Status reg (RO) *)
MacRXFilterWOLClr* = 0FFE00208H; (* Rx Filter WoL Clear reg (WO) *)

MacHASHFilterL* = 0FFE00210H; (* Hash Filter LSBs reg *)
MacHASHFilterH* = 0FFE00214H; (* Hash Filter MSBs reg *)

MacIntStatus* = 0FFE00FE0H; (* Interrupt Status reg (RO) *)
MacIntEnable* = 0FFE00FE4H; (* Interrupt Enable reg  *)
MacIntClear* = 0FFE00FE8H; (* Interrupt Clear reg (WO) *)
MacIntSet* = 0FFE00FECH; (* Interrupt Set reg (WO) *)

MacPOWERDOWN* = 0FFE00FF4H; (* Power-down reg *)
MacModuleID* = 0FFE00FFCH; (* Module ID reg (RO) *)

END LPC2300.