lpc2300.mod

oberon 07 clock for lpc23xx NXP (Philips) chip

MODULE LPC2300;

CONST

VicBaseAddr* = 0FFFFF000H;
VicIrqStatus*= 0FFFFF000H;
VicFiqStatus*= 0FFFFF004H;
ViCrawIntr*= 0FFFFF008H;
VicIntSelect* = 0FFFFF00CH;
VicIntEnable* = 0FFFFF010H;
VicIntEnClr* = 0FFFFF014H;
VicSoftInt* = 0FFFFF018H;
VicSoftIntClr* = 0FFFFF01CH;
VicProtection* = 0FFFFF020H;
VicSwprIoMask* = 0FFFFF024H;

VicVectAddr0* = 0FFFFF100H;
VicVectAddr1* = 0FFFFF104H;
VicVectAddr2* = 0FFFFF108H;
VicVectAddr3* = 0FFFFF10CH;
VicVectAddr4* = 0FFFFF110H;
VicVectAddr5* = 0FFFFF114H;
VicVectAddr6* = 0FFFFF118H;
VicVectAddr7* = 0FFFFF11CH;
VicVectAddr8* = 0FFFFF120H;
VicVectAddr9* = 0FFFFF124H;
VicVectAddr10* = 0FFFFF128H;
VicVectAddr11* = 0FFFFF12CH;
VicVectAddr12* = 0FFFFF130H;
VicVectAddr13* = 0FFFFF134H;
VicVectAddr14* = 0FFFFF138H;
VicVectAddr15* = 0FFFFF13CH;
VicVectAddr16* = 0FFFFF140H;
VicVectAddr17* = 0FFFFF144H;
VicVectAddr18* = 0FFFFF148H;
VicVectAddr19* = 0FFFFF14CH;
VicVectAddr20* = 0FFFFF150H;
VicVectAddr21* = 0FFFFF154H;
VicVectAddr22* = 0FFFFF158H;
VicVectAddr23* = 0FFFFF15CH;
VicVectAddr24* = 0FFFFF160H;
VicVectAddr25* = 0FFFFF164H;
VicVectAddr26* = 0FFFFF168H;
VicVectAddr27* = 0FFFFF16CH;
VicVectAddr28* = 0FFFFF170H;
VicVectAddr29* = 0FFFFF174H;
VicVectAddr30* = 0FFFFF178H;
VicVectAddr31* = 0FFFFF17CH;

(* The name ConvEntIon below is from prevIous LPC2000 family MCUs, in LPC23xx/24xx, these registers are known as "VicVectPrIority(x)". *)
VicVectCntl0* = 0FFFFF200H;
VicVectCntl1* = 0FFFFF204H;
VicVectCntl2* = 0FFFFF208H;
VicVectCntl3* = 0FFFFF20CH;
VicVectCntl4* = 0FFFFF210H;
VicVectCntl5* = 0FFFFF214H;
VicVectCntl6* = 0FFFFF218H;
VicVectCntl7* = 0FFFFF21CH;
VicVectCntl8* = 0FFFFF220H;
VicVectCntl9* = 0FFFFF224H;
VicVectCntl10* = 0FFFFF228H;
VicVectCntl11* = 0FFFFF22CH;
VicVectCntl12* = 0FFFFF230H;
VicVectCntl13* = 0FFFFF234H;
VicVectCntl14* = 0FFFFF238H;
VicVectCntl15* = 0FFFFF23CH;
VicVectCntl16* = 0FFFFF240H;
VicVectCntl17* = 0FFFFF244H;
VicVectCntl18* = 0FFFFF248H;
VicVectCntl19* = 0FFFFF24CH;
VicVectCntl20* = 0FFFFF250H;
VicVectCntl21* = 0FFFFF254H;
VicVectCntl22* = 0FFFFF258H;
VicVectCntl23* = 0FFFFF25CH;
VicVectCntl24* = 0FFFFF260H;
VicVectCntl25* = 0FFFFF264H;
VicVectCntl26* = 0FFFFF268H;
VicVectCntl27* = 0FFFFF26CH;
VicVectCntl28* = 0FFFFF270H;
VicVectCntl29* = 0FFFFF274H;
VicVectCntl30* = 0FFFFF278H;
VicVectCntl31* = 0FFFFF27CH;

VicVectAddr* = 0FFFFFF00H;


(* Pin Connect Block *)
PinSelBaseAddr* = 0E002C000H;
PinSel0* = 0E002C000H;
PinSel1* = 0E002C004H;
PinSel2* = 0E002C008H;
PinSel3* = 0E002C00CH;
PinSel4* = 0E002C010H;
PinSel5* = 0E002C014H;
PinSel6* = 0E002C018H;
PinSel7* = 0E002C01CH;
PinSel8* = 0E002C020H;
PinSel9* = 0E002C024H;
PinSel10* = 0E002C028H;

PinMode0* = 0E002C040H;
PinMode1* = 0E002C044H;
PinMode2* = 0E002C048H;
PinMode3* = 0E002C04CH;
PinMode4* = 0E002C050H;
PinMode5* = 0E002C054H;
PinMode6* = 0E002C058H;
PinMode7* = 0E002C05CH;
PinMode8* = 0E002C060H;
PinMode9* = 0E002C064H;

(* GEneral Purpose Input/Output (GPIo) *)
GPIoBaseAddr* = 0E0028000H;
IoPin0* = 0E0028000H;
IoSet0* = 0E0028004H;
IoDir0* = 0E0028008H;
IoClr0* = 0E002800CH;
IoPin1* = 0E0028010H;
IoSet1* = 0E0028014H;
IoDir1* = 0E0028018H;
IoClr1* = 0E002801CH;

(*PIo Interrupt Registers *)
Io0IntEnR* = 0E0028090H; 
Io0IntEnF* = 0E0028094H;
Io0IntStatR* = 0E0028084H;
Io0IntStatF* = 0E0028088H;
Io0IntClr* = 0E002808CH;

Io2IntEnR* = 0E00280B0H; 
Io2IntEnF* = 0E00280B4H;
Io2IntStatR* = 0E00280A4H;
Io2IntStatF* = 0E00280A8H;
Io2IntClr* = 0E00280ACH;

IoIntStat* = 0E0028080H;

PartcfgBaseAddr* = 03FFF8000H;
Partcfg* = 03FFF8000H;

(* Fast I/O Setup *)
FIoBaseAddr* = 03FFFC000H;
FIo0Dir* = 03FFFC000H; 
FIo0Mask* = 03FFFC010H;
FIo0Pin* = 03FFFC014H;
FIo0Set* = 03FFFC018H;
FIo0Clr* = 03FFFC01CH;

FIo1Dir* = 03FFFC020H; 
FIo1Mask* = 03FFFC030H;
FIo1Pin* = 03FFFC034H;
FIo1Set* = 03FFFC038H;
FIo1Clr* = 03FFFC03CH;

FIo2Dir* = 03FFFC040H; 
FIo2Mask* = 03FFFC050H;
FIo2Pin* = 03FFFC054H;
FIo2Set* = 03FFFC058H;
FIo2Clr* = 03FFFC05CH;

FIo3Dir* = 03FFFC060H; 
FIo3Mask* = 03FFFC070H;
FIo3Pin* = 03FFFC074H;
FIo3Set* = 03FFFC078H;
FIo3Clr* = 03FFFC07CH;

FIo4Dir* = 03FFFC080H; 
FIo4Mask* = 03FFFC090H;
FIo4Pin* = 03FFFC094H;
FIo4Set* = 03FFFC098H;
FIo4Clr* = 03FFFC09CH;

(* FIos Can be accessed through WORD, HALF-WORD or BYTE. *)
FIo0Dir0* = 03FFFC000H; 
FIo1Dir0* = 03FFFC020H; 
FIo2Dir0* = 03FFFC040H; 
FIo3Dir0* = 03FFFC060H; 
FIo4Dir0* = 03FFFC080H; 

FIo0Dir1* = 03FFFC001H; 
FIo1Dir1* = 03FFFC021H; 
FIo2Dir1* = 03FFFC041H; 
FIo3Dir1* = 03FFFC061H; 
FIo4Dir1* = 03FFFC081H; 

FIo0Dir2* = 03FFFC002H; 
FIo1Dir2* = 03FFFC022H; 
FIo2Dir2* = 03FFFC042H; 
FIo3Dir2* = 03FFFC062H; 
FIo4Dir2* = 03FFFC082H; 

FIo0Dir3* = 03FFFC003H; 
FIo1Dir3* = 03FFFC023H; 
FIo2Dir3* = 03FFFC043H; 
FIo3Dir3* = 03FFFC063H; 
FIo4Dir3* = 03FFFC083H; 

FIo0DirL* = 03FFFC000H; 
FIo1DirL* = 03FFFC020H; 
FIo2DirL* = 03FFFC040H; 
FIo3DirL* = 03FFFC060H; 
FIo4DirL* = 03FFFC080H; 

FIo0DirU* = 03FFFC002H; 
FIo1DirU* = 03FFFC022H; 
FIo2DirU* = 03FFFC042H; 
FIo3DirU* = 03FFFC062H; 
FIo4DirU* = 03FFFC082H; 

FIo0Mask0* = 03FFFC010H; 
FIo1Mask0* = 03FFFC030H; 
FIo2Mask0* = 03FFFC050H; 
FIo3Mask0* = 03FFFC070H; 
FIo4Mask0* = 03FFFC090H; 

FIo0Mask1* = 03FFFC011H; 
FIo1Mask1* = 03FFFC021H; 
FIo2Mask1* = 03FFFC051H; 
FIo3Mask1* = 03FFFC071H; 
FIo4Mask1* = 03FFFC091H; 

FIo0Mask2* = 03FFFC012H; 
FIo1Mask2* = 03FFFC032H; 
FIo2Mask2* = 03FFFC052H; 
FIo3Mask2* = 03FFFC072H; 
FIo4Mask2* = 03FFFC092H; 

FIo0Mask3* = 03FFFC013H; 
FIo1Mask3* = 03FFFC033H; 
FIo2Mask3* = 03FFFC053H; 
FIo3Mask3* = 03FFFC073H; 
FIo4Mask3* = 03FFFC093H; 

FIo0MaskL* = 03FFFC010H; 
FIo1MaskL* = 03FFFC030H; 
FIo2MaskL* = 03FFFC050H; 
FIo3MaskL* = 03FFFC070H; 
FIo4MaskL* = 03FFFC090H; 

FIo0MaskU* = 03FFFC012H; 
FIo1MaskU* = 03FFFC032H; 
FIo2MaskU* = 03FFFC052H; 
FIo3MaskU* = 03FFFC072H; 
FIo4MaskU* = 03FFFC092H; 

FIo0Pin0* = 03FFFC014H; 
FIo1Pin0* = 03FFFC034H; 
FIo2Pin0* = 03FFFC054H; 
FIo3Pin0* = 03FFFC074H; 
FIo4Pin0* = 03FFFC094H; 

FIo0Pin1* = 03FFFC015H; 
FIo1Pin1* = 03FFFC025H; 
FIo2Pin1* = 03FFFC055H; 
FIo3Pin1* = 03FFFC075H; 
FIo4Pin1* = 03FFFC095H; 

FIo0Pin2* = 03FFFC016H; 
FIo1Pin2* = 03FFFC036H; 
FIo2Pin2* = 03FFFC056H; 
FIo3Pin2* = 03FFFC076H; 
FIo4Pin2* = 03FFFC096H; 

FIo0Pin3* = 03FFFC017H; 
FIo1Pin3* = 03FFFC037H; 
FIo2Pin3* = 03FFFC057H; 
FIo3Pin3* = 03FFFC077H; 
FIo4Pin3* = 03FFFC097H; 

FIo0PinL* = 03FFFC014H; 
FIo1PinL* = 03FFFC034H; 
FIo2PinL* = 03FFFC054H; 
FIo3PinL* = 03FFFC074H; 
FIo4PinL* = 03FFFC094H; 

FIo0PinU* = 03FFFC016H; 
FIo1PinU* = 03FFFC036H; 
FIo2PinU* = 03FFFC056H; 
FIo3PinU* = 03FFFC076H; 
FIo4PinU* = 03FFFC096H; 

FIo0Set0* = 03FFFC018H; 
FIo1Set0* = 03FFFC038H; 
FIo2Set0* = 03FFFC058H; 
FIo3Set0* = 03FFFC078H; 
FIo4Set0* = 03FFFC098H; 

FIo0Set1* = 03FFFC019H; 
FIo1Set1* = 03FFFC029H; 
FIo2Set1* = 03FFFC059H; 
FIo3Set1* = 03FFFC079H; 
FIo4Set1* = 03FFFC099H; 

FIo0Set2* = 03FFFC01AH; 
FIo1Set2* = 03FFFC03AH; 
FIo2Set2* = 03FFFC05AH; 
FIo3Set2* = 03FFFC07AH; 
FIo4Set2* = 03FFFC09AH; 

FIo0Set3* = 03FFFC01BH; 
FIo1Set3* = 03FFFC03BH; 
FIo2Set3* = 03FFFC05BH; 
FIo3Set3* = 03FFFC07BH; 
FIo4Set3* = 03FFFC09BH; 

FIo0SetL* = 03FFFC018H; 
FIo1SetL* = 03FFFC038H; 
FIo2SetL* = 03FFFC058H; 
FIo3SetL* = 03FFFC078H; 
FIo4SetL* = 03FFFC098H; 

FIo0SetU* = 03FFFC01AH; 
FIo1SetU* = 03FFFC03AH; 
FIo2SetU* = 03FFFC05AH; 
FIo3SetU* = 03FFFC07AH; 
FIo4SetU* = 03FFFC09AH; 

FIo0Clr0* = 03FFFC01CH; 
FIo1Clr0* = 03FFFC03CH; 
FIo2Clr0* = 03FFFC05CH; 
FIo3Clr0* = 03FFFC07CH; 
FIo4Clr0* = 03FFFC09CH; 

FIo0Clr1* = 03FFFC01DH; 
FIo1Clr1* = 03FFFC02DH; 
FIo2Clr1* = 03FFFC05DH; 
FIo3Clr1* = 03FFFC07DH; 
FIo4Clr1* = 03FFFC09DH; 

FIo0Clr2* = 03FFFC01EH; 
FIo1Clr2* = 03FFFC03EH; 
FIo2Clr2* = 03FFFC05EH; 
FIo3Clr2* = 03FFFC07EH; 
FIo4Clr2* = 03FFFC09EH; 

FIo0Clr3* = 03FFFC01FH; 
FIo1Clr3* = 03FFFC03FH; 
FIo2Clr3* = 03FFFC05FH; 
FIo3Clr3* = 03FFFC07FH; 
FIo4Clr3* = 03FFFC09FH; 

FIo0ClrL* = 03FFFC01CH; 
FIo1ClrL* = 03FFFC03CH; 
FIo2ClrL* = 03FFFC05CH; 
FIo3ClrL* = 03FFFC07CH; 
FIo4ClrL* = 03FFFC09CH; 

FIo0ClrU* = 03FFFC01EH; 
FIo1ClrU* = 03FFFC03EH; 
FIo2ClrU* = 03FFFC05EH; 
FIo3ClrU* = 03FFFC07EH; 
FIo4ClrU* = 03FFFC09EH; 


(* System Control Block(SCB) Modules include Memory Accelerator Module,
Phase Locked Loop, VPB Divider, Power Control, External Interrupt, 
ReSet, and Code Security/Debugging *)
SCBBaseAddr* = 0E01FC000H;

(* Memory Accelerator Module (Mam) *)
MamCr* = 0E01FC000H;
MamTim* = 0E01FC004H;
MemMap* = 0E01FC040H;

(* Phase Locked Loop (Pll) *)
PllCon* = 0E01FC080H;
PllCfg* = 0E01FC084H;
PllStat* = 0E01FC088H;
PllFeed* = 0E01FC08CH;

(* Power Control *)
PCon* = 0E01FC0C0H;
PConP* = 0E01FC0C4H;

(* Clock Divider *)
(*)/ APBDiv* = 0E01FC100H;*)
CClkCfg* = 0E01FC104H;
UsbClkCfg* = 0E01FC108H;
ClkSRCSel* = 0E01FC10CH;
PClkSel0* = 0E01FC1A8H;
PClkSel1* = 0E01FC1ACH;
	
(* External Interrupts *)
ExtInt* = 0E01FC140H;
IntWake* = 0E01FC144H;
ExtMode* = 0E01FC148H;
ExtPolar* = 0E01FC14CH;

(* ReSet, reSet source idEntificatIon *)
RSIR* = 0E01FC180H;

(* RSID, code security protectIon *)
CSPR* = 0E01FC184H;

(* Ahb ConfiguratIon *)
AhbCfg1* = 0E01FC188H;
AhbCfg2* = 0E01FC18CH;

(* System Controls and Status *)
SCS* = 0E01FC1A0H;	

(* MPMC(Emc) registers, note: all the External Memory Controller(Emc) registers 
are for LPC24xx only. 
StaticMem0Base* = 080000000H;
StaticMem1Base* = 081000000H;
StaticMem2Base* = 082000000H;
StaticMem3Base* = 083000000H;

DynamicMem0Base* = 0A0000000H;
DynamicMem1Base* = 0B0000000H;
DynamicMem2Base* = 0C0000000H;
DynamicMem3Base* = 0D0000000H;*)

(* External Memory Controller (Emc) *)
EmcBaseAddr* = 0FFE08000H;
EmcCtrl* = 0FFE08000H;
EmcStat* = 0FFE08004H;
EmcConfig* = 0FFE08008H;

(* Dynamic RAM access registers *)
EmcDynCtrl* = 0FFE08020H;
EmcDynRFSH* = 0FFE08024H;
EmcDynRDCfg* = 0FFE08028H;
EmcDynRP* = 0FFE08030H;
EmcDynRAS* = 0FFE08034H;
EmcDynSREX* = 0FFE08038H;
EmcDynAPR* = 0FFE0803CH;
EmcDynDAL* = 0FFE08040H;
EmcDynWR* = 0FFE08044H;
EmcDynRC* = 0FFE08048H;
EmcDynRFC* = 0FFE0804CH;
EmcDynXSR* = 0FFE08050H;
EmcDynRRD* = 0FFE08054H;
EmcDynMRD* = 0FFE08058H;

EmcDynCfg0* = 0FFE08100H;
EmcDynRASCAS0* = 0FFE08104H;
EmcDynCfg1* = 0FFE08140H;
EmcDynRASCAS1* = 0FFE08144H;
EmcDynCfg2* = 0FFE08160H;
EmcDynRASCAS2* = 0FFE08164H;
EmcDynCfg3* = 0FFE08180H;
EmcDynRASCAS3* = 0FFE08184H;

(* Static RAM access registers *)
EmcStaCfg0* = 0FFE08200H;
EmcStaWaitWEn0* = 0FFE08204H;
EmcStaWaitOEn0* = 0FFE08208H;
EmcStaWaitRD0* = 0FFE0820CH;
EmcStaWaitPAGE0* = 0FFE08210H;
EmcStaWaitWR0* = 0FFE08214H;
EmcStaWaitTURN0* = 0FFE08218H;

EmcStaCfg1* = 0FFE08220H;
EmcStaWaitWEn1* = 0FFE08224H;
EmcStaWaitOEn1* = 0FFE08228H;
EmcStaWaitRD1* = 0FFE0822CH;
EmcStaWaitPAGE1* = 0FFE08230H;
EmcStaWaitWR1* = 0FFE08234H;
EmcStaWaitTURN1* = 0FFE08238H;

EmcStaCfg2* = 0FFE08240H;
EmcStaWaitWEn2* = 0FFE08244H;
EmcStaWaitOEn2* = 0FFE08248H;
EmcStaWaitRD2* = 0FFE0824CH;
EmcStaWaitPAGE2* = 0FFE08250H;
EmcStaWaitWR2* = 0FFE08254H;
EmcStaWaitTURN2* = 0FFE08258H;

EmcStaCfg3* = 0FFE08260H;
EmcStaWaitWEn3* = 0FFE08264H;
EmcStaWaitOEn3* = 0FFE08268H;
EmcStaWaitRD3* = 0FFE0826CH;
EmcStaWaitPAGE3* = 0FFE08270H;
EmcStaWaitWR3* = 0FFE08274H;
EmcStaWaitTURN3* = 0FFE08278H;

EmcStaExtWait* = 0FFE08880H;

	
(* Timer 0 *)
TMR0BaseAddr* = 0E0004000H;
T0IR* = 0E0004000H;
T0TCr* = 0E0004004H;
T0TC* = 0E0004008H;
T0PR* = 0E000400CH;
T0PC* = 0E0004010H;
T0MCr* = 0E0004014H;
T0MR0* = 0E0004018H;
T0MR1* = 0E000401CH;
T0MR2* = 0E0004020H;
T0MR3* = 0E0004024H;
T0CCr* = 0E0004028H;
T0Cr0* = 0E000402CH;
T0Cr1* = 0E0004030H;
T0Cr2* = 0E0004034H;
T0Cr3* = 0E0004038H;
T0EMR* = 0E000403CH;
T0CTCr* = 0E0004070H;

(* Timer 1 *)
TMR1BaseAddr* = 0E0008000H;
T1IR* = 0E0008000H;
T1TCr* = 0E0008004H;
T1TC* = 0E0008008H;
T1PR* = 0E000800CH;
T1PC* = 0E0008010H;
T1MCr* = 0E0008014H;
T1MR0* = 0E0008018H;
T1MR1* = 0E000801CH;
T1MR2* = 0E0008020H;
T1MR3* = 0E0008024H;
T1CCr* = 0E0008028H;
T1Cr0* = 0E000802CH;
T1Cr1* = 0E0008030H;
T1Cr2* = 0E0008034H;
T1Cr3* = 0E0008038H;
T1EMR* = 0E000803CH;
T1CTCr* = 0E0008070H;

(* Timer 2 *)
TMR2BaseAddr* = 0E0070000H;
T2IR* = 0E0070000H;
T2TCr* = 0E0070004H;
T2TC* = 0E0070008H;
T2PR* = 0E007000CH;
T2PC* = 0E0070010H;
T2MCr* = 0E0070014H;
T2MR0* = 0E0070018H;
T2MR1* = 0E007001CH;
T2MR2* = 0E0070020H;
T2MR3* = 0E0070024H;
T2CCr* = 0E0070028H;
T2Cr0* = 0E007002CH;
T2Cr1* = 0E0070030H;
T2Cr2* = 0E0070034H;
T2Cr3* = 0E0070038H;
T2EMR* = 0E007003CH;
T2CTCr* = 0E0070070H;

(* Timer 3 *)
TMR3BaseAddr* = 0E0074000H;
T3IR* = 0E0074000H;
T3TCr* = 0E0074004H;
T3TC* = 0E0074008H;
T3PR* = 0E007400CH;
T3PC* = 0E0074010H;
T3MCr* = 0E0074014H;
T3MR0* = 0E0074018H;
T3MR1* = 0E007401CH;
T3MR2* = 0E0074020H;
T3MR3* = 0E0074024H;
T3CCr* = 0E0074028H;
T3Cr0* = 0E007402CH;
T3Cr1* = 0E0074030H;
T3Cr2* = 0E0074034H;
T3Cr3* = 0E0074038H;
T3EMR* = 0E007403CH;