📄 dp_rx_drv.c
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dp_rx_lvds_dual_single = 0x10;
for(i = 0; i < 12; i++)
dp_rx_lvds_mapping[i] = i;
DP_RX_WriteI2C_RX0(PWD_REG, 0x6f);
DP_RX_Set_FW_State(STATE_WAIT_HPD);
DP_RX_WriteI2C_RX0(INTR_MASK_1, 0xff);
DP_RX_WriteI2C_RX0(INTR_MASK_2, 0xff);
DP_RX_WriteI2C_RX0(INTR_MASK_3, 0xff);
DP_RX_WriteI2C_RX0(INTR_MASK_4, 0xff);
//lllll, ????? if(S2_2)
// DP_RX_WriteI2C_RX0(0x1f,0x01);
DP_RX_WriteI2C_RX0(0x1f,0x00);
}
void DP_RX_Interrupt_Debug_Info(BYTE c, BYTE n)
{
/*
switch (n)
{
case 1:
if (c & 0x01)
B_puts("Int info: Reserved.");
if (c & 0x02)
B_puts("Int info: Link bandwidth changed");
if (c & 0x04)
B_puts("Int info: Video format changed.");
if (c & 0x08)
B_puts("Int info: I2C master has error.");
if (c & 0x10)
B_puts("Int info: AUX CH has error.");
if (c & 0x20)
B_puts("Int info: Stream clock PLL has un-locked.");
if (c & 0x40)
B_puts("Int info: Link clock recovery error and has un-lock indicator.");
if (c & 0x80)
B_puts("Int info: InfoFram can not be recognize.");
break;
case 2:
if (c & 0x01)
B_puts("Int info: cable unplugged.");
if (c & 0x02)
B_puts("Int info: interlaced status.");
if (c & 0x04)
B_puts("Int info: SYNC polarity haschanged.");
if (c & 0x08)
B_puts("Int info: horizontal resolution changed.");
if (c & 0x10)
B_puts("Int info: vertical resolution has changed.");
if (c & 0x20)
B_puts("Int info: MPEG InforFram has changed");
if (c & 0x40)
B_puts("Int info: AVI InforFram has changed");
if (c & 0x80)
B_puts("Int info: SPD InforFram has changed.");
break;
case 3:
if (c & 0x01)
B_puts("Int info: MCCS/EDID transaction from source.");
if (c & 0x02)
B_puts("Int info: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~Clock recovery training pattern. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
if (c & 0x04)
B_puts("Int info: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~Equalization training pattern~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .");
if (c & 0x08)
B_puts("Int info: D10.2 test pattern.");
if (c & 0x10)
B_puts("Int info: Error rate measurement pattern.");
if (c & 0x20)
B_puts("Int info: PRBS 7 test pattern.");
if (c & 0x40)
B_puts("Int info: VSYNC has detected.");
if (c & 0x80)
B_puts("Int info: Reserved.");
break;
case 4:
if (c & 0x01)
B_puts("Int info: HDCP_SHA_READY.");
if (c & 0x02)
B_puts("Int info: main attribute data lose.");
if (c & 0x04)
B_puts("Int info: The major voting error of VB_ID or Mvid or Maud.");
if (c & 0x08)
B_puts("Int info: FIFO error.");
if (c & 0x10)
B_puts("Int info: HDCP_AUTH_OK.");
if (c & 0x20)
B_puts("Int info: HDCP_AUTH_START.");
if (c & 0x40)
B_puts("Int info: HDCP_LINK_FAILURE.");
if (c & 0x80)
B_puts("Int info: HDCP_R0_AVAILABLE.");
break;
}
*/
}
void DP_RX_Show_Vid_Info(void)
{
/* BYTE c,cv;
long int M_val,N_val,str_clk,temp;
// horizontal resolution
DP_RX_ReadI2C_RX0(ACT_PIX_HIGH, &cv);
s_dp_rx.cur_h_res = (cv<<8);
DP_RX_ReadI2C_RX0(ACT_PIX_LOW, &cv);
s_dp_rx.cur_h_res += cv;
// vertical resoltuion
DP_RX_ReadI2C_RX0(ACT_LINE_HIGH, &cv);
s_dp_rx.cur_v_res = (cv<<8);
DP_RX_ReadI2C_RX0(ACT_LINE_LOW, &cv);
s_dp_rx.cur_v_res += cv;
B_puts("*********************** Show Chip Info *************************");
DP_RX_ReadI2C_RX1(LINK_BW_SET, &c);
if(c == LINK_1D62G)
{
B_puts("The link bandwidth is 1.62G.");
str_clk = 162;
}
else
{
B_puts("The link bandwidth is 2.7G.");
str_clk = 270;
}
// stream clock
DP_RX_ReadI2C_RX0(M_FORCE_VALUE_3, &cv);
M_val = cv * 0x10000;
DP_RX_ReadI2C_RX0(M_FORCE_VALUE_2, &cv);
M_val = cv * 0x100;
DP_RX_ReadI2C_RX0(M_FORCE_VALUE_1, &cv);
M_val = M_val + cv;
DP_RX_ReadI2C_RX0(N_FORCE_VALUE_3, &cv);
N_val = cv * 0x10000;
DP_RX_ReadI2C_RX0(N_FORCE_VALUE_2, &cv);
N_val = cv * 0x100;
DP_RX_ReadI2C_RX0(N_FORCE_VALUE_1, &cv);
N_val = N_val + cv;
str_clk = str_clk * M_val;
str_clk = str_clk / N_val;
debug_printf("Input stream clock = %lu, M = %lu, N = %lu\n",str_clk,M_val,N_val);
// video type is progressive or interlace
DP_RX_ReadI2C_RX0(SYNC_STATUS, &cv);
if(cv & 0x04)
{
B_puts("Video format is interlace.");
s_dp_rx.cur_v_res *= 2;
}
else
{
B_puts("Video format is progressive.");
}
debug_printf("Recover Resolution is %d * %d \n",
s_dp_rx.cur_h_res,s_dp_rx.cur_v_res);
B_puts("Counting link error for one second...");
DP_RX_8B10B_Err_Chk(1);
B_puts("-----------------------------------------------------------");
DP_RX_ReadI2C_RX0(0x1f, &c);
if(c&0x01)
B_puts("Source detection(0x50:0x1f) detects High");
else
B_puts("Source detection(0x50:0x1f) detects Low");
DP_RX_ReadI2C_RX0(0x13, &c);
if(c&0x08)
B_puts("(0x50:0x13) No video stream is transported.");
// horizontal total
DP_RX_ReadI2C_RX0(0x24, &c);
h_total_main = c;
h_total_main = h_total_main << 8;
DP_RX_ReadI2C_RX0(0x25, &c);
h_total_main = h_total_main+c;
//v total
DP_RX_ReadI2C_RX0(0x2e, &c);
v_total_main = c;
v_total_main = v_total_main << 8;
DP_RX_ReadI2C_RX0(0x2f, &c);
v_total_main = v_total_main+c;
//hsync width
DP_RX_ReadI2C_RX0(0x22, &c);
if(c&0x80)
B_puts("HSYNC polarity is Negative");
else
B_puts("HSYNC polarity is Positive");
hsync_wid_main = c & 0x7f;
hsync_wid_main = hsync_wid_main << 8;
DP_RX_ReadI2C_RX0(0x23, &c);
hsync_wid_main = hsync_wid_main+c;
//vsync width
DP_RX_ReadI2C_RX0(0x2c, &c);
if(c&0x80)
B_puts("VSYNC polarity is Negative");
else
B_puts("VSYNC polarity is Positive");
vsync_wid_main = c & 0x7f;
vsync_wid_main = vsync_wid_main << 8;
DP_RX_ReadI2C_RX0(0x2d, &c);
vsync_wid_main = vsync_wid_main+c;
//h_bp
DP_RX_ReadI2C_RX0(0x20, &c);
temp = c;
temp = temp << 8;
DP_RX_ReadI2C_RX0(0x21, &c);
temp = temp+c;
h_bp_main = temp - hsync_wid_main;
//v_bp
DP_RX_ReadI2C_RX0(0x2a, &c);
temp = c;
temp = temp << 8;
DP_RX_ReadI2C_RX0(0x2b, &c);
temp = temp+c;
v_bp_main = temp - vsync_wid_main;
// horizontal resolution
DP_RX_ReadI2C_RX0(0x26, &c);
h_main = c;
h_main = h_main << 8;
DP_RX_ReadI2C_RX0(0x27, &c);
h_main = h_main+c;
// vertical resoltuion
DP_RX_ReadI2C_RX0(0x28, &c);
v_main = c;
v_main = v_main<<8;;
DP_RX_ReadI2C_RX0(0x29, &c);
v_main = v_main+c;
//h_fp
h_fp_main = h_total_main - (h_main + h_bp_main + hsync_wid_main);
//v_fp
v_fp_main = v_total_main - (v_main + v_bp_main + vsync_wid_main);
debug_printf("Active Resolution from Main Attribute is %d * %d \n",h_main, v_main);
debug_printf("Total Resolution from Main Attribute is %d * %d \n",h_total_main, v_total_main);
debug_printf("HSYNC width from Main Attribute is %d \n",hsync_wid_main);
debug_printf("H_front porch from Main Attribute is %d \n",h_fp_main);
debug_printf("H_back porch from Main Attribute is %d \n",h_bp_main);
debug_printf("VSYNC width from Main Attribute is %d \n",vsync_wid_main);
debug_printf("V_front porch from Main Attribute is %d \n",v_fp_main);
debug_printf("V_back porch from Main Attribute is %d \n",v_bp_main);
DP_RX_ReadI2C_RX0(0xc3,&c);
if(c&0x04)
B_puts("(0x50:0xc3) AUX CH request timeout(>200us)");
if(c&0x02)
B_puts("AUX CH Manchester II decode error");
if(c&0x01)
B_puts("AUX CH request length error");
if((c & 0x07)==0)
B_puts("(0x50:0xc3) AUX CH no error");
DP_RX_ReadI2C_RX0(0xc4,&c);
if(c&0x04)
B_puts("(0x50:0xc4) I2C master received No ACK");
if(c&0x02)
B_puts("I2C master is free");
else
B_puts("I2C master is busy");
if(c&0x01)
B_puts("I2C master lost arbitrary");
DP_RX_ReadI2C_RX0(0xda,&c);
debug_printf("(0x50:0xda) BOOST1_CH0 = %.2x\n", (WORD)((c>>3)&0x07));
debug_printf("(0x50:0xda) BOOST1_CH1 = %.2x\n", (WORD)(c&0x07));
DP_RX_ReadI2C_RX0(0xdb,&c);
debug_printf("(0x50:0xdb) BOOST1_CH2 = %.2x\n", (WORD)((c>>3)&0x07));
debug_printf("(0x50:0xdb) BOOST1_CH3 = %.2x\n", (WORD)(c&0x07));
DP_RX_ReadI2C_RX0(0xdc,&c);
debug_printf("(0x50:0xdc) BOOST2_CH0 = %.2x\n", (WORD)((c>>3)&0x07));
debug_printf("(0x50:0xdc) BOOST2_CH1 = %.2x\n", (WORD)(c&0x07));
DP_RX_ReadI2C_RX0(0xdd,&c);
debug_printf("(0x50:0xdd) BOOST2_CH2 = %.2x\n", (WORD)((c>>3)&0x07));
debug_printf("(0x50:0xdd) BOOST2_CH3 = %.2x\n", (WORD)(c&0x07));
DP_RX_ReadI2C_RX0(0xde,&c);
debug_printf("(0x50:0xde) GAIN1_CH0 = %.2x\n", (WORD)((c>>3)&0x03));
debug_printf("(0x50:0xde) GAIN1_CH1 = %.2x\n", (WORD)(c&0x03));
DP_RX_ReadI2C_RX0(0xdf,&c);
debug_printf("(0x50:0xdf) GAIN1_CH2 = %.2x\n", (WORD)((c>>3)&0x03));
debug_printf("(0x50:0xdf) GAIN1_CH3 = %.2x\n", (WORD)(c&0x03));
DP_RX_ReadI2C_RX0(0xe7,&c);
debug_printf("(0x50:0xe7) GAIN2_CH0 = %.2x\n", (WORD)((c>>3)&0x03));
debug_printf("(0x50:0xe7) GAIN2_CH1 = %.2x\n", (WORD)(c&0x03));
DP_RX_ReadI2C_RX0(0xe8,&c);
debug_printf("(0x50:0xe8) GAIN2_CH2 = %.2x\n", (WORD)((c>>3)&0x03));
debug_printf("(0x50:0xe8) GAIN2_CH3 = %.2x\n", (WORD)(c&0x03));
B_puts("*****************************************************************");
*/}
void DP_RX_Cable_Lost_Int(void)
{
DP_RX_WriteI2C_RX0(PWD_REG,0x80);
DP_RX_Set_FW_State(STATE_WAIT_HPD);
B_puts("HPD Lost, power down DP lanes.");
// Interrupt register mask configuration.
DP_RX_WriteI2C_RX0(INTR_MASK_1, 0xff);
DP_RX_WriteI2C_RX0(INTR_MASK_2, 0xff);
DP_RX_WriteI2C_RX0(INTR_MASK_3, 0xff);
DP_RX_WriteI2C_RX0(INTR_MASK_4, 0xff);
DP_RX_HPD(0);
}
void DP_RX_Vid_Change_Int(void)
{
if((DP_Rx_fw_state != STATE_WAIT_HPD) && (DP_Rx_fw_state != STATE_CHK_LINK))
{
B_puts("Video format is changed.");
//DP_RX_Mute_Vid();
DP_RX_Set_FW_State(STATE_WAIT_VIDEO);
}
}
void DP_RX_Link_Err_Int(void)
{
if((DP_Rx_fw_state != STATE_WAIT_HPD) && (DP_Rx_fw_state != STATE_CHK_LINK))
{
B_puts("link is unstable.");
DP_RX_Set_FW_State(STATE_WAIT_VIDEO);
}
}
void DP_RX_Data_RCV_Int(void)
{
if((DP_Rx_fw_state != STATE_WAIT_VIDEO) && (DP_Rx_fw_state != STATE_PLAY_BACK))
{
DP_RX_WriteI2C_RX0(PWD_REG, 0x00);
DP_RX_WriteI2C_RX0(INTR_MASK_3, 0xf9);
DP_RX_Set_FW_State(STATE_WAIT_VIDEO);
DP_RX_WriteI2C_RX0(INTR_MASK_1, 0xf9);
}
}
void DP_RX_Set_FW_State(BYTE fw_state)
{
DP_Rx_fw_state = fw_state;
//debug_printf("DP_RX ");
switch (DP_Rx_fw_state)
{
case STATE_WAIT_HPD:
B_puts("to sys state STATE_WAIT_HPD");
break;
case STATE_CHK_LINK:
B_puts("to sys state STATE_CHK_LINK");
break;
case STATE_WAIT_VIDEO:
B_puts("to sys state STATE_WAIT_VIDEO");
break;
case STATE_PLAY_BACK:
B_puts("to sys state STATE_PLAY_BACK");
break;
default:
break;
}
}
void DP_RX_UnMute_Vid(void)
{
BYTE cv;
DP_RX_ReadI2C_RX0(SYSTEM_CTRL_3, &cv);
DP_RX_WriteI2C_RX0(SYSTEM_CTRL_3, (cv & 0xef));
B_puts("DP_RX: Un-mute video.");
}
void DP_RX_Mute_Vid(void)
{
BYTE cv;
DP_RX_ReadI2C_RX0(SYSTEM_CTRL_3, &cv);
DP_RX_WriteI2C_RX0(SYSTEM_CTRL_3, (cv | 0x10));
B_puts("DP_RX: Video is muted.");
}
void DP_RX_LVDS_Output_Mapping(BYTE to_hw_lvds_channel, BYTE from_rx_internal_channel)
{
BYTE c;
switch(to_hw_lvds_channel)
{
case 0:
DP_RX_ReadI2C_RX0(LVDS_SWAP_0_1, &c);
DP_RX_WriteI2C_RX0(LVDS_SWAP_0_1, c & 0x0f | (from_rx_internal_channel << 4));
break;
case 1:
DP_RX_ReadI2C_RX0(LVDS_SWAP_0_1, &c);
DP_RX_WriteI2C_RX0(LVDS_SWAP_0_1, c & 0xf0 | from_rx_internal_channel);
break;
case 2:
DP_RX_ReadI2C_RX0(LVDS_SWAP_2_3, &c);
DP_RX_WriteI2C_RX0(LVDS_SWAP_2_3, c & 0x0f | (from_rx_internal_channel << 4));
break;
case 3:
DP_RX_ReadI2C_RX0(LVDS_SWAP_2_3, &c);
DP_RX_WriteI2C_RX0(LVDS_SWAP_2_3, c & 0xf0 | from_rx_internal_channel);
break;
case 4:
DP_RX_ReadI2C_RX0(LVDS_SWAP_4_5, &c);
DP_RX_WriteI2C_RX0(LVDS_SWAP_4_5, c & 0x0f | (from_rx_internal_channel << 4));
break;
case 5:
DP_RX_ReadI2C_RX0(LVDS_SWAP_4_5, &c);
DP_RX_WriteI2C_RX0(LVDS_SWAP_4_5, c & 0xf0 | from_rx_internal_channel);
break;
case 6:
DP_RX_ReadI2C_RX0(LVDS_SWAP_6_7, &c);
DP_RX_WriteI2C_RX0(LVDS_SWAP_6_7, c & 0x0f | (from_rx_internal_channel << 4));
break;
case 7:
DP_RX_ReadI2C_RX0(LVDS_SWAP_6_7, &c);
DP_RX_WriteI2C_RX0(LVDS_SWAP_6_7, c & 0xf0 | from_rx_internal_channel);
break;
case 8:
DP_RX_ReadI2C_RX0(LVDS_SWAP_8_9, &c);
DP_RX_WriteI2C_RX0(LVDS_SWAP_8_9, c & 0x0f | (from_rx_internal_channel << 4));
break;
case 9:
DP_RX_ReadI2C_RX0(LVDS_SWAP_8_9, &c);
DP_RX_WriteI2C_RX0(LVDS_SWAP_8_9, c & 0xf0 | from_rx_internal_channel);
break;
case 10:
DP_RX_ReadI2C_RX0(LVDS_SWAP_10_11, &c);
DP_RX_WriteI2C_RX0(LVDS_SWAP_10_11, c & 0x0f | (from_rx_internal_channel << 4));
break;
case 11:
DP_RX_ReadI2C_RX0(LVDS_SWAP_10_11, &c);
DP_RX_WriteI2C_RX0(LVDS_SWAP_10_11, c & 0xf0 | from_rx_internal_channel);
break;
default:
break;
}
}
//**************** I2C routines ********************
BYTE DP_RX_ReadI2C_RX0(BYTE offset, BYTE *rxdata)
{
BYTE rc;
EX1 = 0;
i2c_dev_addr = DP_Rx_PORT0_ADDR;
rc = i2c_read_reg(offset, rxdata);
return rc;
}
BYTE DP_RX_WriteI2C_RX0(BYTE offset, BYTE txdata)
{
BYTE rc;
EX1 = 0;
i2c_dev_addr = DP_Rx_PORT0_ADDR;
rc = i2c_write_reg(offset, txdata);
return rc;
}
BYTE DP_RX_ReadI2C_RX1(BYTE offset, BYTE *rxdata)
{
BYTE rc;
EX1 = 0;
i2c_dev_addr = DP_Rx_PORT1_ADDR;
rc = i2c_read_reg(offset, rxdata);
return rc;
}
BYTE DP_RX_WriteI2C_RX1(BYTE offset, BYTE txdata)
{
BYTE rc;
EX1 = 0;
i2c_dev_addr = DP_Rx_PORT1_ADDR;
rc = i2c_write_reg(offset, txdata);
return rc;
}
BYTE DP_RX_ReadI2C_RX2(BYTE offset, BYTE *rxdata)
{
BYTE rc;
EX1 = 0;
i2c_dev_addr = DP_Rx_PORT2_ADDR;
rc = i2c_read_reg(offset, rxdata);
return rc;
}
BYTE DP_RX_WriteI2C_RX2(BYTE offset, BYTE txdata)
{
BYTE rc;
EX1 = 0;
i2c_dev_addr = DP_Rx_PORT2_ADDR;
rc = i2c_write_reg(offset, txdata);
return rc;
}
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