📄 dp_rx_drv.lst
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280 1 if(cv & 0x80)
281 1 {
282 2 delay_ms(20);
283 2 DP_RX_ReadI2C_RX0(SYSTEM_STATUS_1, &cv);
284 2 if(cv & 0x80)
285 2 {
286 3 DP_RX_InitSys();
287 3
288 3 if(1) // test without EDID reading, lllll
289 3 {
290 4 DP_RX_WriteI2C_RX0(PWD_REG, 0x00);
291 4 DP_RX_WriteI2C_RX0(INTR_MASK_3, 0xf9);
292 4 B_puts("Testing with equiment without EDID reading");
293 4 DP_RX_Set_FW_State(STATE_WAIT_VIDEO);
294 4 DP_RX_WriteI2C_RX0(INTR_MASK_1, 0xf9);
295 4 }
296 3 else
297 3 DP_RX_Set_FW_State(STATE_CHK_LINK);
298 3
299 3 DP_RX_HPD(1);
300 3 EX_EN = 1;
301 3
302 3 }
C51 COMPILER V7.50 DP_RX_DRV 10/03/2008 17:53:10 PAGE 6
303 2 }
304 1
305 1
306 1 }
307
308
309 // check the main stream attribute
310 void DP_RX_Wait_Video(void)
311 {
312 1 BOOL pass = 1;
313 1 BYTE cv;
314 1
315 1 if(DP_RX_Link_Stable() == 0)
316 1 {
317 2 pass = 0;
318 2 B_puts("DP_RX: link is unstable.");
319 2 return;
320 2 }
321 1
322 1 if (DP_RX_Stream_Attr_Stable() == 0)
323 1 {
324 2 pass = 0;
325 2 B_puts("DP_RX: Main stream attribute error.");
326 2 return;
327 2 }
328 1
329 1 // is video active
330 1 // debug_printf("DP_RX: Check video active: ");
331 1 DP_RX_ReadI2C_RX0(SYSTEM_STATUS_2, &cv);
332 1 if(cv & 0x08)
333 1 {
334 2 B_puts("Link is stable.");
335 2 pass = 1;
336 2 }
337 1 else
338 1 {
339 2 pass = 0;
340 2 B_puts("Link is not stable.");
341 2 return;
342 2 }
343 1
344 1 if(pass)
345 1 {
346 2 DP_RX_UnMute_Vid();
347 2 EX1 = 0;
348 2 if(DP_Rx_fw_state == STATE_WAIT_VIDEO)
349 2 DP_RX_Set_FW_State(STATE_PLAY_BACK);
350 2
351 2 DP_RX_Show_Vid_Info();
352 2 }
353 1
354 1 }
355
356 // Link maintenance
357 void DP_RX_PlayBack(void)
358 {
359 1 DP_RX_SL_CR_AL_State_Checking();
360 1 }
361
362
363 // check if the link is ok
364 BOOL DP_RX_Link_Stable(void)
C51 COMPILER V7.50 DP_RX_DRV 10/03/2008 17:53:10 PAGE 7
365 {
366 1 BYTE c,cv;
367 1 BOOL lane3_en,lane2_en,lane1_en,lane0_en;
368 1
369 1 lane3_en = 0;
370 1 lane2_en = 0;
371 1 lane1_en = 0;
372 1 lane0_en = 0;
373 1
374 1 DP_RX_ReadI2C_RX1(LANE_COUNT_SET, &c);
375 1 c = c & 0x0f;
376 1 if(c == 0x04)
377 1 {
378 2 lane3_en = 1;
379 2 lane2_en = 1;
380 2 lane1_en = 1;
381 2 lane0_en = 1;
382 2 }
383 1 else if(c == 0x02)
384 1 {
385 2 lane1_en = 1;
386 2 lane0_en = 1;
387 2 }
388 1 else if(c == 0x01)
389 1 lane0_en = 1;
390 1
391 1 DP_RX_ReadI2C_RX0(SYSTEM_STATUS_1, &cv);
392 1
393 1 // check HPD, crystal clk and Serdes Pll lock
394 1 if( (cv & 0x04) != 0x04)
395 1 {
396 2 B_puts("PLL not lock.");
397 2 return 0;
398 2 }
399 1
400 1 // check lane 3 and lane 2 sync status
401 1
402 1 if(lane3_en)
403 1 {
404 2 if( (cv & 0x02) != 0x02)
405 2 {
406 3 B_puts("No sync in Lane3.");
407 3 return 0;
408 3 }
409 2 }
410 1 if(lane2_en)
411 1 {
412 2 if( (cv & 0x01) != 0x01)
413 2 {
414 3 B_puts("No sync in Lane2.");
415 3 return 0;
416 3 }
417 2 }
418 1
419 1 // check sync status of lane 1 and lane 0
420 1 DP_RX_ReadI2C_RX0(SYSTEM_STATUS_2, &cv);
421 1 if(lane1_en)
422 1 {
423 2 if( (cv & 0x80) != 0x80)
424 2 {
425 3 B_puts("No sync in Lane1.");
426 3 return 0;
C51 COMPILER V7.50 DP_RX_DRV 10/03/2008 17:53:10 PAGE 8
427 3 }
428 2 }
429 1 if(lane0_en)
430 1 {
431 2 if( (cv & 0x40) != 0x40)
432 2 {
433 3 B_puts("No sync in Lane0.");
434 3 return 0;
435 3 }
436 2 }
437 1
438 1 // check Align status
439 1 if((cv & 0x20) == 0x20)
440 1 {
441 2 B_puts("Channel align stable!");
442 2 return 1;
443 2 }
444 1 else
445 1 {
446 2 return 0;
447 2 }
448 1
449 1 }
450
451 // check if the main stream attributes is ok
452 BOOL DP_RX_Stream_Attr_Stable(void)
453 {
454 1 BYTE cv;
455 1
456 1 DP_RX_ReadI2C_RX0(SYSTEM_STATUS_2, &cv);
457 1 if((cv & 0x04) == 0x04 )
458 1 {
459 2 return 1;
460 2 }
461 1 else
462 1 {
463 2 return 0;
464 2 }
465 1
466 1 }
467
468 BOOL DP_RX_Chip_Located(void)
469 {
470 1 BYTE c,c0,i;
471 1
472 1 for(i = 0; i < 10; i++)
473 1 {
474 2 DP_RX_HW_Reset();
475 2 DP_RX_ReadI2C_RX0(VENDOR_ID_L, &c);
476 2 DP_RX_ReadI2C_RX0(VENDOR_ID_H, &c0);
477 2 if((c == 0x85) && (c0 == 0x14))
478 2 break;
479 2 }
480 1 if(i < 10)
481 1 return 1;
482 1 else
483 1 {
484 2 B_puts("\n Can not read registers from DP RX, something wrong with I2C or chip.");
485 2 enable_debug_output = 0;
486 2 return 0;
487 2 }
488 1 }
C51 COMPILER V7.50 DP_RX_DRV 10/03/2008 17:53:10 PAGE 9
489
490 // init globe variables
491 void DP_RX_Init_Var(void)
492 {
493 1 BYTE i;
494 1 s_dp_rx.cur_h_res = 0;
495 1 s_dp_rx.cur_v_res = 0;
496 1 dp_rx_lanecount = 4;
497 1 dp_rx_bandwidth = 0x0a;
498 1 dp_rx_lvds_format = 0x00;
499 1 dp_rx_lvds_dual_single = 0x10;
500 1 for(i = 0; i < 12; i++)
501 1 dp_rx_lvds_mapping[i] = i;
502 1 DP_RX_WriteI2C_RX0(PWD_REG, 0x6f);
503 1 DP_RX_Set_FW_State(STATE_WAIT_HPD);
504 1 DP_RX_WriteI2C_RX0(INTR_MASK_1, 0xff);
505 1 DP_RX_WriteI2C_RX0(INTR_MASK_2, 0xff);
506 1 DP_RX_WriteI2C_RX0(INTR_MASK_3, 0xff);
507 1 DP_RX_WriteI2C_RX0(INTR_MASK_4, 0xff);
508 1
509 1 //lllll, ????? if(S2_2)
510 1 // DP_RX_WriteI2C_RX0(0x1f,0x01);
511 1 DP_RX_WriteI2C_RX0(0x1f,0x00);
512 1 }
513
514 void DP_RX_Interrupt_Debug_Info(BYTE c, BYTE n)
515 {
516 1 /*
517 1 switch (n)
518 1 {
519 1 case 1:
520 1 if (c & 0x01)
521 1 B_puts("Int info: Reserved.");
522 1 if (c & 0x02)
523 1 B_puts("Int info: Link bandwidth changed");
524 1 if (c & 0x04)
525 1 B_puts("Int info: Video format changed.");
526 1 if (c & 0x08)
527 1 B_puts("Int info: I2C master has error.");
528 1 if (c & 0x10)
529 1 B_puts("Int info: AUX CH has error.");
530 1 if (c & 0x20)
531 1 B_puts("Int info: Stream clock PLL has un-locked.");
532 1 if (c & 0x40)
533 1 B_puts("Int info: Link clock recovery error and has un-lock indicator.");
534 1 if (c & 0x80)
535 1 B_puts("Int info: InfoFram can not be recognize.");
536 1 break;
537 1 case 2:
538 1 if (c & 0x01)
539 1 B_puts("Int info: cable unplugged.");
540 1 if (c & 0x02)
541 1 B_puts("Int info: interlaced status.");
542 1 if (c & 0x04)
543 1 B_puts("Int info: SYNC polarity haschanged.");
544 1
545 1 if (c & 0x08)
546 1 B_puts("Int info: horizontal resolution changed.");
547 1 if (c & 0x10)
548 1 B_puts("Int info: vertical resolution has changed.");
549 1
550 1
C51 COMPILER V7.50 DP_RX_DRV 10/03/2008 17:53:10 PAGE 10
551 1
552 1 if (c & 0x20)
553 1 B_puts("Int info: MPEG InforFram has changed");
554 1 if (c & 0x40)
555 1 B_puts("Int info: AVI InforFram has changed");
556 1 if (c & 0x80)
557 1 B_puts("Int info: SPD InforFram has changed.");
558 1 break;
559 1 case 3:
560 1 if (c & 0x01)
561 1 B_puts("Int info: MCCS/EDID transaction from source.");
562 1 if (c & 0x02)
563 1 B_puts("Int info: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~Clock recovery training pattern. ~~~~~~~~~~~~~~~
-~~~~~~~~~~~~~~~");
564 1 if (c & 0x04)
565 1 B_puts("Int info: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~Equalization training pattern~~~~~~~~~~~~~~~~~~~
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