📄 dp_rx_drv.lst
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C51 COMPILER V7.50 DP_RX_DRV 10/03/2008 17:53:10 PAGE 1
C51 COMPILER V7.50, COMPILATION OF MODULE DP_RX_DRV
OBJECT MODULE PLACED IN ..\hex\DP_RX_DRV.obj
COMPILER INVOKED BY: D:\Program Files\KEIL_UV3\C51\BIN\C51.EXE DP_RX_DRV.c LARGE OPTIMIZE(SIZE) BROWSE DEBUG OBJECTEXTEN
-D CODE OBJECT(..\hex\DP_RX_DRV.obj)
line level source
1 // *******************************************
2
3 // *******************************************
4
5 #include "DP_RX_DRV.h"
6 #include "i2c_intf.h"
7 #include "mcu.h"
8 #include "timer.h"
9
10 // globe variables
11 e_DP_Rx_FW_STATE DP_Rx_fw_state;
12 s_DP_Rx_CUR_STATE s_dp_rx;
13
14 BYTE timer_slot ;
15 BYTE dp_rx_lanecount;
16 BYTE dp_rx_bandwidth;
17 BYTE dp_rx_lvds_format;
18 BYTE dp_rx_lvds_dual_single;
19 BYTE dp_rx_lvds_mapping[12];
20 WORD h_main,v_main;
21 WORD h_total_main,v_total_main;
22 WORD hsync_wid_main,vsync_wid_main;
23 WORD h_bp_main,v_bp_main;
24 WORD h_fp_main,v_fp_main;
25 bit fix;
26
27 void DP_RX_MainTask(void)
28 {
29 1 DP_RX_Timer_Process();
30 1 //lllll,
31 1 #if Disable_interrupt
32 1 DP_RX_Interrupt_Process();
33 1 #endif
34 1 }
35
36 void DP_RX_Timer_Process(void)
37 {
38 1 DP_RX_Timer_slot1();
39 1 DP_RX_Timer_slot2();
40 1 }
41
42 // handler all interrupts
43 void DP_RX_Interrupt_Process(void)
44 {
45 1 BYTE cv,int1,int2,int3,int4;
46 1
47 1 if (DP_Rx_fw_state != STATE_WAIT_HPD)
48 1 {
49 2 DP_RX_ReadI2C_RX0(INTR_4, &int4);
50 2 DP_RX_WriteI2C_RX0(INTR_4, ~int4);
51 2 if((int4 & 0x80) ||(int4 & 0x40))
52 2 {
53 3 B_puts("R0' available or HDCP link failed!");
54 3 DP_RX_ReadI2C_RX1(IRQ_VECTOR, &cv);
C51 COMPILER V7.50 DP_RX_DRV 10/03/2008 17:53:10 PAGE 2
55 3 if(cv & 0x04)//if TX not clear this bit
56 3 {
57 4 DP_RX_HPD(0);
58 4 delay_half_ms();//delay 0.5ms
59 4 DP_RX_HPD(1);
60 4 }
61 3 }
62 2 DP_RX_ReadI2C_RX0(INTR_3, &int3);
63 2 DP_RX_WriteI2C_RX0(INTR_3, ~int3);
64 2 if(int3 & 0x01)
65 2 DP_RX_Data_RCV_Int();
66 2
67 2 DP_RX_ReadI2C_RX0(INTR_1, &int1);
68 2 DP_RX_WriteI2C_RX0(INTR_1, ~int1);
69 2
70 2 DP_RX_ReadI2C_RX0(INTR_2, &int2);
71 2 DP_RX_WriteI2C_RX0(INTR_2, ~int2);
72 2
73 2 if(int2 & 0x01)
74 2 DP_RX_Cable_Lost_Int();
75 2
76 2 if(int1 & 0x04)
77 2 DP_RX_Vid_Change_Int();
78 2
79 2 if(int1 & 0x02)
80 2 DP_RX_Link_Err_Int();
81 2
82 2 DP_RX_Interrupt_Debug_Info(int1, 1);
83 2 DP_RX_Interrupt_Debug_Info(int2, 2);
84 2 DP_RX_Interrupt_Debug_Info(int3, 3);
85 2 DP_RX_Interrupt_Debug_Info(int4, 4);
86 2 }
87 1 }
88
89 // main state machine in firmware
90 void DP_RX_Timer_slot1(void)
91 {
92 1
93 1 if(DP_Rx_fw_state == STATE_WAIT_HPD)
94 1 DP_RX_CHK_Cable();
95 1 if(DP_Rx_fw_state == STATE_CHK_LINK)
96 1 DP_RX_CHK_Link();
97 1 if(DP_Rx_fw_state == STATE_WAIT_VIDEO)
98 1 DP_RX_Wait_Video();
99 1 }
100
101 void DP_RX_Timer_slot2(void)
102 {
103 1 if(DP_Rx_fw_state == STATE_PLAY_BACK)
104 1 DP_RX_PlayBack();
105 1
106 1 }
107
108 void DP_RX_SL_CR_AL_State_Checking(void)
109 {
110 1 BYTE cLane_cnt,cstat1,cstat2;
111 1
112 1 //for align status
113 1 DP_RX_ReadI2C_RX0(SYSTEM_STATUS_2, &cstat2);
114 1 if((cstat2 & 0x20) != 0x20)
115 1 {
116 2 B_puts("align loss");
C51 COMPILER V7.50 DP_RX_DRV 10/03/2008 17:53:10 PAGE 3
117 2 DP_RX_HPD_Update_Status();
118 2 }
119 1 else
120 1 {
121 2 //for symbol and clock loss
122 2 DP_RX_ReadI2C_RX1(LANE_COUNT_SET, &cLane_cnt);
123 2 if((cLane_cnt & 0x0f) == 0x04)//4lane used
124 2 {
125 3 DP_RX_ReadI2C_RX0(SYSTEM_STATUS_1, &cstat1);
126 3 DP_RX_ReadI2C_RX0(SYSTEM_STATUS_2, &cstat2);
127 3
128 3 if(((cstat1&0x03)!=0x03)||((cstat2&0xc0)!=0xc0))
129 3 {
130 4 B_puts("sl and cr loss");
131 4 DP_RX_HPD_Update_Status();
132 4 }
133 3 }
134 2 else if(((cLane_cnt & 0x0f) == 0x02)||((cLane_cnt & 0x0f) == 0x01))
135 2 {
136 3 DP_RX_ReadI2C_RX0(SYSTEM_STATUS_2, &cstat1);
137 3 if((cLane_cnt & 0x0f) == 0x02)////2lane used
138 3 {
139 4 if((cstat2 &0xc0)!=0xc0)
140 4 {
141 5 B_puts("sl and cr loss");
142 5 DP_RX_HPD_Update_Status();
143 5 }
144 4 }
145 3 else//1lane used
146 3 {
147 4 if((cstat2 & 0x40)!=0x40)
148 4 {
149 5 B_puts("sl and cr loss");
150 5 DP_RX_HPD_Update_Status();
151 5 }
152 4 }
153 3 }
154 2 }
155 1 }
156
157 void DP_RX_HPD_Update_Status(void)
158 {
159 1 BYTE c;
160 1 EX1 = 0;
161 1
162 1 DP_RX_Set_FW_State(STATE_WAIT_VIDEO);
163 1 DP_RX_WriteI2C_RX0(INTR_MASK_3, 0xfd);
164 1 DP_RX_ReadI2C_RX1(TRAINING_PATTERN_SET, &c);
165 1 DP_RX_WriteI2C_RX1(TRAINING_PATTERN_SET, c |0x02);
166 1 //IRQ HPD
167 1 DP_RX_HPD(0);
168 1 delay_half_ms();//delay 0.5ms
169 1 DP_RX_HPD(1);
170 1 DP_RX_WriteI2C_RX0(INTR_MASK_3, 0xf9);
171 1
172 1 }
173
174 void DP_RX_Set_Lane_Count(BYTE lanecount)
175 {
176 1 BYTE c;
177 1 DP_RX_ReadI2C_RX1(MAX_LINE_COUNT, &c);
178 1 DP_RX_WriteI2C_RX1(MAX_LINE_COUNT, c & 0xf0 |lanecount);
C51 COMPILER V7.50 DP_RX_DRV 10/03/2008 17:53:10 PAGE 4
179 1 DP_RX_WriteI2C_RX1(LANE_COUNT_SET, lanecount);
180 1 }
181
182 void DP_RX_Set_BandWidth(BYTE bandwidth)
183 {
184 1 DP_RX_WriteI2C_RX1(MAX_LINE_RATE, bandwidth);
185 1 DP_RX_WriteI2C_RX1(LINK_BW_SET, bandwidth);
186 1 }
187
188 void DP_RX_Set_LVDS_Format(BYTE format)
189 {
190 1 BYTE c;
191 1 DP_RX_ReadI2C_RX0(LVDS_CTRL_3, &c);
192 1 DP_RX_WriteI2C_RX0(LVDS_CTRL_3, (c & 0xf3) | format);
193 1 }
194
195 void DP_RX_Set_LVDS_Dual_Single(BYTE dual_signal)
196 {
197 1 BYTE c;
198 1 DP_RX_ReadI2C_RX0(VID_CTRL_1, &c);
199 1 DP_RX_WriteI2C_RX0(VID_CTRL_1, (c & 0xef) | dual_signal);
200 1 }
201
202 void DP_RX_CHK_Link(void)
203 {
204 1 BYTE c;
205 1 DP_RX_ReadI2C_RX0(SYSTEM_STATUS_2,&c);
206 1 if(c & 0x03)
207 1 {
208 2 DP_RX_WriteI2C_RX0(PWD_REG, 0x00);
209 2 DP_RX_WriteI2C_RX0(INTR_MASK_3, 0xf9);
210 2 B_puts("AUX CMD found");
211 2 DP_RX_Set_FW_State(STATE_WAIT_VIDEO);
212 2 DP_RX_WriteI2C_RX0(INTR_MASK_1, 0xf9);
213 2 DP_RX_WriteI2C_RX0(SYSTEM_STATUS_2,c);
214 2 }
215 1 }
216
217 // power up chip, init the registers
218 void DP_RX_InitSys(void)
219 {
220 1 BYTE c;
221 1
222 1 DP_RX_WriteI2C_RX0(PWD_REG, 0x6f);
223 1 DP_RX_WriteI2C_RX0(SFT_RST_REG, 0x40);
224 1
225 1 DP_RX_WriteI2C_RX0(SFT_RST_AUTO_REG, 0x38);
226 1
227 1 DP_RX_WriteI2C_RX0(GPIO_CTRL, 0x42);
228 1
229 1 DP_RX_WriteI2C_RX0(TM_LOOP_CTRL_1, 0x05);
230 1
231 1 DP_RX_WriteI2C_RX0(EQ_TAIN_CTRL1, 0x9a);
232 1
233 1 //enable AVC
234 1 DP_RX_ReadI2C_RX0(SYSTEM_CTRL_3,&c);
235 1 DP_RX_WriteI2C_RX0(SYSTEM_CTRL_3, (c | 0x08));
236 1
237 1
238 1 //config HDCP
239 1 DP_RX_WriteI2C_RX1(SINK_COUNT, 0x40);
240 1 //DP_RX_WriteI2C_RX1(BCAPS, 0x01);
C51 COMPILER V7.50 DP_RX_DRV 10/03/2008 17:53:10 PAGE 5
241 1 DP_RX_WriteI2C_RX1(MAX_LINE_COUNT, 0x84);
242 1 DP_RX_WriteI2C_RX0(SYSTEM_CTRL_1, 0x00);
243 1 DP_RX_WriteI2C_RX0(SYSTEM_CTRL_2, 0x08);
244 1
245 1 //scramble select
246 1 // DP_RX_WriteI2C_RX1(MAIN_LINK_CHANNEL_CODING, 0x09);
247 1 DP_RX_WriteI2C_RX1(MAIN_LINK_CHANNEL_CODING, 0x0f);
248 1
249 1 DP_RX_Mute_Vid();
250 1
251 1 DP_RX_WriteI2C_RX0(INTR_MASK_1, 0xff);
252 1 DP_RX_WriteI2C_RX0(INTR_MASK_2, 0xfe);
253 1 DP_RX_WriteI2C_RX0(INTR_MASK_3, 0xf8);
254 1 DP_RX_WriteI2C_RX0(INTR_MASK_4, 0x3f);
255 1
256 1 //set int. output type
257 1 DP_RX_WriteI2C_RX0(INTR_CTRL, 0x01);
258 1
259 1 DP_RX_Set_Lane_Count(dp_rx_lanecount);
260 1 DP_RX_Set_BandWidth(dp_rx_bandwidth);
261 1 DP_RX_Set_LVDS_Format(dp_rx_lvds_format);
262 1 DP_RX_Set_LVDS_Dual_Single(dp_rx_lvds_dual_single);
263 1 for(c = 0; c < 12; c++)
264 1 DP_RX_LVDS_Output_Mapping(c, dp_rx_lvds_mapping[c]);
265 1 //power on LVDS
266 1 DP_RX_WriteI2C_RX0(LVDS_PD_1, 0x00);
267 1 DP_RX_WriteI2C_RX0(LVDS_PD_2, 0x00);
268 1 //lllll, ??????
269 1 // DP_RX_WriteI2C_RX0(0x1f,0x01);
270 1 DP_RX_WriteI2C_RX0(0x1f,0x00);
271 1
272 1 }
273
274 // cable plug
275 void DP_RX_CHK_Cable(void)
276 {
277 1 BYTE cv;
278 1 EX1 = 0;
279 1 DP_RX_ReadI2C_RX0(SYSTEM_STATUS_1, &cv);
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