📄 dp_rx_drv.h
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// *******************************************
// *******************************************
#ifndef DP_Rx_h
#define DP_Rx_h
#include <stdio.h>
#include <stdarg.h>
#include "mcu.h"
// config macros
#define USE_MCU
#define SIM
#define DP_Rx_FW_VER 1.05
// DP_RX hardware reset pin
#define DP_Rx_HW_RESET P2_2 //lllll
#define DP_RX_HPD_DET P2_3 //lllll,
// i2c address
#define DP_Rx_PORT0_ADDR 0x50
#define DP_Rx_PORT1_ADDR 0x8c
#define DP_Rx_PORT2_ADDR 0x98
// link bandwidth
#define LINK_1D62G 0x06
#define LINK_2D7G 0x0a
// variable type macros
typedef unsigned char BYTE;
typedef bit BOOL;
typedef unsigned int WORD;
// firmware states
typedef enum
{
STATE_WAIT_HPD,
STATE_CHK_LINK,
STATE_WAIT_VIDEO,
STATE_PLAY_BACK
} e_DP_Rx_FW_STATE;
extern e_DP_Rx_FW_STATE DP_Rx_fw_state;
extern BYTE dp_rx_lanecount;
extern BYTE dp_rx_bandwidth;
extern BYTE dp_rx_lvds_format;
extern BYTE dp_rx_lvds_dual_single;
extern BYTE dp_rx_lvds_mapping[12];
extern bit fix;
typedef enum
{
TTL_OUT,
LVDS_OUT
};
#define RGB_Sep_Sync 0x00
#define RGB_Sep_Sync_60b 0x04
typedef struct tag_dp_rx
{
WORD cur_v_res;
WORD cur_h_res;
} s_DP_Rx_CUR_STATE;
// routines
void DP_RX_Timer_Process(void);
void DP_RX_Interrupt_Process(void);
void DP_RX_MainTask();
void DP_RX_CHK_Link(void);
void DP_RX_Timer_slot1(void);
void DP_RX_Timer_slot2(void);
void DP_RX_CHK_Cable(void);
void DP_RX_Set_FW_State(BYTE fw_state);
void DP_RX_InitSys(void);
void DP_RX_Wait_Video(void);
void DP_RX_PlayBack(void);
BOOL DP_RX_Link_Stable(void);
BOOL DP_RX_Stream_Attr_Stable(void);
BOOL DP_RX_AVI_Stable(void);
BOOL DP_RX_Chip_Located(void);
void DP_RX_Init_Var(void);
void DP_RX_Interrupt_Debug_Info(BYTE c, BYTE n);
void DP_RX_UnMute_Vid(void);
void DP_RX_Mute_Vid(void);
void DP_RX_Show_Vid_Info(void);
void DP_RX_Cable_Lost_Int(void);
void DP_RX_Vid_Change_Int(void);
void DP_RX_Link_Err_Int(void);
void DP_RX_Data_RCV_Int(void);
BOOL DP_RX_Video_Vormat_Change(void);
void DP_RX_Set_Lane_Count(BYTE lanecount);
void DP_RX_Set_BandWidth(BYTE bandwidth);
void DP_RX_Set_LVDS_Format(BYTE format);
void DP_RX_SL_CR_AL_State_Checking(void);
void DP_RX_HPD_Update_Status(void);
void DP_RX_LVDS_Output_Mapping(BYTE to_hw_lvds_channel, BYTE from_rx_internal_channel);
void DP_RX_Set_LVDS_Dual_Single(BYTE dual_signal);
// I2C routines
BYTE DP_RX_ReadI2C_RX0(BYTE offset, BYTE *rxdata);
BYTE DP_RX_WriteI2C_RX0(BYTE offset, BYTE txdata);
BYTE DP_RX_ReadI2C_RX1(BYTE offset, BYTE *rxdata);
BYTE DP_RX_WriteI2C_RX1(BYTE offset, BYTE txdata);
BYTE DP_RX_ReadI2C_RX2(BYTE offset, BYTE *rxdata);
BYTE DP_RX_WriteI2C_RX2(BYTE offset, BYTE txdata);
//void DP_Rx_State_Vid_TTL(void);
#define fix_1280x1024 0
#define fix_2560x1600 1
// registers definition
// i2c address 0x50 or 0x52
#define VENDOR_ID_L 0x00
#define VENDOR_ID_H 0x01
#define DEVICE_ID_L 0x02
#define DEVICE_ID_H 0x03
#define DEVICE_VERSION 0x04
#define SFT_RST_AUTO_REG 0x05
#define SFT_RST_REG 0x06
#define PWD_REG 0x07
#define SYSTEM_CTRL_1 0x08
#define SYSTEM_CTRL_2 0x09
#define SYSTEM_CTRL_3 0x0a
#define SYSTEM_STATUS_1 0x0b
#define STATUS_1_HPD 0x80 //bit
#define SYSTEM_STATUS_2 0x0c
#define M_FORCE_VALUE_3 0x0d
#define M_FORCE_VALUE_2 0x0e
#define M_FORCE_VALUE_1 0x0F
#define N_FORCE_VALUE_3 0x10
#define N_FORCE_VALUE_2 0x11
#define N_FORCE_VALUE_1 0x12
#define VB_ID_INFOR 0x13
#define RC_TRAINING_RESULT 0x14
#define PRBS_CTRL 0x15
#define DITHER_CTRL 0x16
#define RCD_PN_CONVERTE 0x17
#define LANE_USE_AS 0x18
#define I2C_MASTER_SPEED_CTRL 0x19
#define INFORFRAM_STATUS 0x1a
#define MAIN_HSTART_1 0x20
#define MAIN_HSTART_2 0x21
#define MAIN_HSW_1 0x22
#define MAIN_HSW_2 0x23
#define MAIN_HTOTAL_1 0x24
#define MAIN_HTOTAL_2 0x25
#define MAIN_HWIDTH_1 0x26
#define MAIN_HWIDTH_2 0x27
#define MAIN_VHEIGHT_1 0x28
#define MAIN_VHEIGHT_2 0x29
#define MAIN_VSTART_1 0x2a
#define MAIN_VSTART_2 0x2b
#define MAIN_VSW_1 0x2c
#define MAIN_VSW_2 0x2d
#define MAIN_VTOTAL_1 0x2e
#define MAIN_VTOTAL_2 0x2f
#define MISC_CTRL_ATTRI 0x30
#define TU_ACTIVE_SYMBOL 0x31
#define FIFO_READ_POINTER_TH_1 0x32
#define FIFO_READ_POINTER_PRE_1 0x33
#define FIFO_READ_POINTER_TH_2 0x34
#define FIFO_READ_POINTER_PRE_2 0x35
#define FIFO_READ_POINTER_TH_3 0x36
#define FIFO_READ_POINTER_PRE_3 0x37
#define FIFO_READ_POINTER_TH_4 0x38
#define FIFO_READ_POINTER_PRE_4 0x39
#define FIFO_READ_POINTER_TH_5 0x3a
#define FIFO_READ_POINTER_PRE_5 0x3b
#define FIFO_READ_POINTER_TH_6 0x3c
#define FIFO_READ_POINTER_PRE_6 0x3d
#define FIFO_READ_POINTER_TH_7 0x3e
#define FIFO_READ_POINTER_PRE_7 0x3f
#define FIFO_READ_POINTER_PRE_8 0x40
#define FIFO_READ_POINTER_PRE_9 0x41
#define FIFO_READ_POINTER_PRE_10 0x42
#define FIFO_READ_POINTER_PRE_11 0x43
#define FIFO_READ_POINTER_PRE_12 0x44
#define FIFO_READ_POINTER_PRE_13 0x45
#define FIFO_READ_POINTER_PRE_14 0x46
#define FIFO_READ_POINTER_PRE_15 0x47
#define FIFO_READ_POINTER_PRE_16 0x48
#define FIFO_READ_POINTER_PRE_17 0x49
#define FIFO_READ_POINTER_PRE_18 0x4a
#define FIFO_READ_POINTER_PRE_19 0x4b
#define FIFO_READ_POINTER_PRE_20 0x4c
#define REG_MISC_CTRL 0x4d
#define LINK_LAYER_STATE_1 0x4e
#define LINK_LAYER_STATE_2 0x4f
#define AVI_Info_byte1 0x50
#define AVI_Info_byte2 0x51
#define AVI_Info_byte3 0x52
#define AVI_Info_byte4 0x53
#define AVI_Info_byte5 0x54
#define AVI_Info_byte6 0x55
#define AVI_Info_byte7 0x56
#define AVI_Info_byte8 0x57
#define AVI_Info_byte9 0x58
#define AVI_Info_byte10 0x59
#define AVI_Info_byte11 0x5a
#define AVI_Info_byte12 0x5b
#define AVI_Info_byte13 0x5c
#define AVI_Info_byte14 0x5d
#define AVI_Info_byte15 0x5e
#define AVI_Info_byte16 0x5f
#define MS_Info_byte1 0x60
#define MS_Info_byte2 0x61
#define MS_Info_byte3 0x62
#define MS_Info_byte4 0x63
#define MS_Info_byte5 0x64
#define MS_Info_byte6 0x65
#define MS_Info_byte7 0x66
#define MS_Info_byte8 0x67
#define MS_Info_byte9 0x68
#define MS_Info_byte10 0x69
#define MS_Info_byte11 0x6a
#define MS_Info_byte12 0x6b
#define MS_Info_byte13 0x6c
#define SPD_Info_byte1 0x6d
#define SPD_Info_byte2 0x6e
#define SPD_Info_byte3 0x6f
#define SPD_Info_byte4 0x70
#define SPD_Info_byte5 0x71
#define SPD_Info_byte6 0x72
#define SPD_Info_byte7 0x73
#define SPD_Info_byte8 0x74
#define SPD_Info_byte9 0x75
#define SPD_Info_byte10 0x76
#define SPD_Info_byte11 0x77
#define SPD_Info_byte12 0x78
#define SPD_Info_byte13 0x79
#define SPD_Info_byte14 0x7a
#define SPD_Info_byte15 0x7b
#define SPD_Info_byte16 0x7c
#define SPD_Info_byte17 0x7d
#define SPD_Info_byte18 0x7e
#define SPD_Info_byte19 0x7f
#define SPD_Info_byte20 0x80
#define SPD_Info_byte21 0x81
#define SPD_Info_byte22 0x82
#define SPD_Info_byte23 0x83
#define SPD_Info_byte24 0x84
#define SPD_Info_byte25 0x85
#define SPD_Info_byte26 0x86
#define SPD_Info_byte27 0x87
#define SPD_Info_byte28 0x88
#define MAIN_ATTR_CTRL_1 0x89
#define MAIN_ATTR_CTRL_2 0x8a
#define SS_OTHER_HEADER 0x8b
#define NEW_TU_NUM 0x8c
#define H_RES_LOW 0x90
#define H_RES_HIGH 0x91
#define V_RES_LOW 0x92
#define V_RES_HIGH 0x93
#define ACT_PIX_LOW 0x94
#define ACT_PIX_HIGH 0x95
#define ACT_LINE_LOW 0x96
#define ACT_LINE_HIGH 0x97
#define VSYNC_TO_ACT_LINE 0x98
#define ACT_LINE_TO_VSYNC 0x99
#define SYNC_STATUS 0x9a
#define H_F_PORCH_LOW 0x9b
#define H_F_PORCH_HIGH 0x9c
#define HSYNC_WIDTH_LOW 0x9d
#define HSYNC_WIDTH_HIGH 0x9e
#define VID_CTRL_1 0x9f
#define VID_CTRL_2 0xa0
#define BLANK_DATA_1 0xa1
#define BLANK_DATA_2 0xa2
#define BLANK_DATA_3 0xa3
#define EQ_TAIN_CTRL1 0xa4
#define MATRIX_BIT_0 0xa5
#define MATRIX_BIT_1 0xa6
#define MATRIX_BIT_2 0xa7
#define MATRIX_BIT_3 0xa8
#define MATRIX_BIT_4 0xa9
#define MATRIX_BIT_5 0xaa
#define MATRIX_BIT_6 0xab
#define MATRIX_BIT_7 0xac
#define MATRIX_BIT_8 0xad
#define MATRIX_BIT_9 0xae
#define MATRIX_BIT_10 0xaf
#define MATRIX_BIT_11 0xb0
#define MATRIX_BIT_12 0xb1
#define MATRIX_BIT_13 0xb2
#define MATRIX_BIT_14 0xb3
#define MATRIX_BIT_15 0xb4
#define MATRIX_BIT_16 0xb5
#define MATRIX_BIT_17 0xb6
#define MATRIX_BIT_18 0xb7
#define MATRIX_BIT_19 0xb8
#define MATRIX_BIT_20 0xb9
#define MATRIX_BIT_21 0xba
#define MATRIX_BIT_22 0xbb
#define MATRIX_BIT_23 0xbc
#define MATRIX_BIT_24 0xbd
#define MATRIX_BIT_25 0xbe
#define MATRIX_BIT_26 0xbf
#define MATRIX_BIT_27 0xc0
#define MATRIX_BIT_28 0xc1
#define MATRIX_BIT_29 0xc2
#define AUX_CH_STATUS 0xc3
#define I2C_MASTER_STATUS 0xc4
#define INTR_CTRL 0xc6
#define INTR_STATUS 0xc7
#define INTR_1 0xc8
#define INTR_2 0xc9
#define INTR_3 0xca
#define INTR_4 0xcb
#define INTR_MASK_1 0xcc
#define INTR_MASK_2 0xcd
#define INTR_MASK_3 0xce
#define INTR_MASK_4 0xcf
#define DEBUG_DATA_OUT_SEL 0xd0
#define GPIO_CTRL 0xd1
#define DEBUG_DATA 0xd2
#define PIX_CLK_CNT 0xd3
#define SOFT_DEBUG 0xef
#define PLL_CTRL_1 0xd4
#define PLL_CTRL_2 0xd5
#define EQ_LOWPASS_CTRL 0xd6
#define SERDES_TEST_CTRL 0xd7
#define RX_TERM_CTRL 0xd8
#define EQ_VCOM_CTRL 0xd9
#define BOOST1_CH0_1 0xda
#define BOOST1_CH2_3 0xdb
#define BOOST2_CH0_1 0xdc
#define BOOST2_CH2_3 0xdd
#define GAIN1_CH0_1 0xde
#define GAIN1_CH2_3 0xdf
#define GAIN2_CH0_1 0xe7
#define GAIN2_CH2_3 0xe8
#define DLL_OFFSET_CH0_1 0xe9
#define DLL_OFFSET_CH2_3 0xea
#define TM_LOOP_CTRL_1 0xeb
#define TM_LOOP_CTRL_2 0xec
#define TM_LOOP_CTRL_3 0xed
#define AUX_TX_TERM 0xee
#define F_PLL_AUTO_ADJ 0xf0
#define F_PLL_CTRL 0xf1
#define F_PLL_TEST 0xf2
#define LVDS_PD_1 0xf3
#define LVDS_PD_2 0xf4
#define LVDS_CTRL_1 0xf5
#define LVDS_CTRL_2 0xf6
#define LVDS_TEST 0xf7
#define LVDS_CTRL_3 0xf8
#define LVDS_SWAP_0_1 0xf9
#define LVDS_SWAP_2_3 0xfa
#define LVDS_SWAP_4_5 0xfb
#define LVDS_SWAP_6_7 0xfc
#define LVDS_SWAP_8_9 0xfd
#define LVDS_SWAP_10_11 0xfe
#define LVDS_CK1_PAT 0x1b
#define LVDS_CK2_PAT 0x1c
#define HDCP_RESET_CTRL 0x1f
#define SOURCE_DET_SEL_HIGH 0x01
// i2c address 0x8c or 0x8e
#define DPCD_REV 0x01
#define MAX_LINE_RATE 0x02
#define MAX_LINE_COUNT 0x03
#define NORP 0x04
#define DOWNSTRAMPORT_PRESENT 0x05
#define RECEIVE_PORT0_CAP_0 0x06
#define RECEIVE_PORT0_CAP_1 0x07
#define MAIN_LINK_CHANNEL_CODING 0x08
#define MAIN_LINK_CHANNEL_CODING_SET 0x09
#define LINK_BW_SET 0x0a
#define LANE_COUNT_SET 0x0b
#define TRAINING_PATTERN_SET 0x0c
#define TRAINING_LANE0_SET 0x0d
#define TRAINING_LANE1_SET 0x0e
#define TRAINING_LANE2_SET 0x0f
#define TRAINING_LANE3_SET 0x10
#define LANE0_1_STATUS 0x11
#define LANE2_3_STATUS 0x12
#define LANE_ALIGH_STUTUS_UPDATED 0x13
#define SINK_STATUS 0x14
#define ADJUST_REQUEST_LANE0_1 0x15
#define ADJUST_REQUEST_LANE2_3 0x16
#define SYMBOL_ERROR_COUNT_LANE0_0 0x17
#define SYMBOL_ERROR_COUNT_LANE0_1 0x18
#define SYMBOL_ERROR_COUNT_LANE1_0 0x19
#define SYMBOL_ERROR_COUNT_LANE1_1 0x1a
#define SYMBOL_ERROR_COUNT_LANE2_0 0x1b
#define SYMBOL_ERROR_COUNT_LANE2_1 0x1c
#define SYMBOL_ERROR_COUNT_LANE3_0 0x1d
#define SYMBOL_ERROR_COUNT_LANE3_1 0x1e
#define PRBS7_STATE_OUT 0x1f
#define PRBS7_ERR_CNT_0_3 0x20
#define PRBS7_ERR_CNT_0_2 0x21
#define SINK_COUNT 0x22
#define BCAPS 0x66
#define PRBS7_ERR_CNT_0_0 0x23
#define PRBS7_ERR_CNT_1_3 0x24
#define PRBS7_ERR_CNT_1_2 0x25
#define PRBS7_ERR_CNT_1_1 0x26
#define PRBS7_ERR_CNT_1_0 0x27
#define PRBS7_ERR_CNT_2_3 0x28
#define PRBS7_ERR_CNT_2_2 0x29
#define PRBS7_ERR_CNT_2_1 0x2a
#define PRBS7_ERR_CNT_2_0 0x2b
#define PRBS7_ERR_CNT_3_3 0x2c
#define PRBS7_ERR_CNT_3_2 0x2d
#define PRBS7_ERR_CNT_3_1 0x2e
#define IRQ_VECTOR 0x2f
#define PRBS7_ERR_IND 0x30
#define LANE_USE_CONFIG 0x31
#define PRBS_STATE_OUT 0x32
#define PRBS_ERR_CNT_0_3 0x33
#define PRBS_ERR_CNT_0_2 0x34
#define PRBS_ERR_CNT_0_1 0x35
#define PRBS_ERR_CNT_0_0 0x36
#define PRBS_ERR_CNT_1_3 0x37
#define PRBS_ERR_CNT_1_2 0x38
#define PRBS_ERR_CNT_1_1 0x39
#define PRBS_ERR_CNT_1_0 0x3a
#define PRBS_ERR_CNT_2_3 0x3b
#define PRBS_ERR_CNT_2_2 0x3c
#define PRBS_ERR_CNT_2_1 0x3d
#define PRBS_ERR_CNT_2_0 0x3e
#define PRBS_ERR_CNT_3_3 0x3f
#define PRBS_ERR_CNT_3_2 0x40
#define PRBS_ERR_CNT_3_1 0x41
#define PRBS_ERR_CNT_3_0 0x42
#define PRBS_ERR_IND 0x43
#define AUX_CH_SET 0x44
#define SLA_ADDR 0xe1
#define OP_LENGTH_WR 0xe2
#define FIFO_DATA_OUT 0xe3
#define OP_REPLY_LEN 0xe4
#define FIFO_DATA_IN 0xe5
#endif
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