stopwatch.map.rpt

vhdl stopwatch -quartus2

; seg_com[5]~reg0                        ; 4       ;
; Total number of inverted registers = 7 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 256:1              ; 7 bits    ; 1190 LEs      ; 14 LEs               ; 1176 LEs               ; No         ; |stopwatch|Mux6            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_divide:Mod0 ;
+------------------------+----------------+------------------------+
; Parameter Name         ; Value          ; Type                   ;
+------------------------+----------------+------------------------+
; LPM_WIDTHN             ; 7              ; Untyped                ;
; LPM_WIDTHD             ; 7              ; Untyped                ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                ;
; LPM_PIPELINE           ; 0              ; Untyped                ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                ;
; CBXI_PARAMETER         ; lpm_divide_65m ; Untyped                ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY             ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY           ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE           ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE         ;
+------------------------+----------------+------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_divide:Div0 ;
+------------------------+----------------+------------------------+
; Parameter Name         ; Value          ; Type                   ;
+------------------------+----------------+------------------------+
; LPM_WIDTHN             ; 7              ; Untyped                ;
; LPM_WIDTHD             ; 4              ; Untyped                ;
; LPM_NREPRESENTATION    ; UNSIGNED       ; Untyped                ;
; LPM_DREPRESENTATION    ; UNSIGNED       ; Untyped                ;
; LPM_PIPELINE           ; 0              ; Untyped                ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                ;
; MAXIMIZE_SPEED         ; 5              ; Untyped                ;
; CBXI_PARAMETER         ; lpm_divide_0dm ; Untyped                ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY             ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY           ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE           ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE         ;
+------------------------+----------------+------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition
    Info: Processing started: Fri Dec 05 11:45:06 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off stopwatch -c stopwatch
Info: Found 2 design units, including 1 entities, in source file stopwatch.vhd
    Info: Found design unit 1: stopwatch-arc
    Info: Found entity 1: stopwatch
Info: Elaborating entity "stopwatch" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at stopwatch.vhd(50): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at stopwatch.vhd(57): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at stopwatch.vhd(65): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at stopwatch.vhd(80): signal "sw23" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at stopwatch.vhd(82): signal "sw33" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at stopwatch.vhd(89): signal "sw13" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at stopwatch.vhd(90): signal "break" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at stopwatch.vhd(77): inferring latch(es) for signal or variable "break", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "break" at stopwatch.vhd(77)
Info: Inferred 2 megafunctions from design logic
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Mod0"
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Div0"
Info: Elaborated megafunction instantiation "lpm_divide:Mod0"
Info: Instantiated megafunction "lpm_divide:Mod0" with the following parameter:
    Info: Parameter "LPM_WIDTHN" = "7"
    Info: Parameter "LPM_WIDTHD" = "7"
    Info: Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
    Info: Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_65m.tdf
    Info: Found entity 1: lpm_divide_65m
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_dkh.tdf
    Info: Found entity 1: sign_div_unsign_dkh
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_sve.tdf
    Info: Found entity 1: alt_u_div_sve
Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf
    Info: Found entity 1: add_sub_lkc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf
    Info: Found entity 1: add_sub_mkc
Info: Elaborated megafunction instantiation "lpm_divide:Div0"
Info: Instantiated megafunction "lpm_divide:Div0" with the following parameter:
    Info: Parameter "LPM_WIDTHN" = "7"
    Info: Parameter "LPM_WIDTHD" = "4"
    Info: Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
    Info: Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_0dm.tdf
    Info: Found entity 1: lpm_divide_0dm
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_akh.tdf
    Info: Found entity 1: sign_div_unsign_akh
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_mve.tdf
    Info: Found entity 1: alt_u_div_mve
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "seg[7]" is stuck at GND
Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below.
    Info: Register "sw12" lost all its fanouts during netlist optimizations.
    Info: Register "sw11" lost all its fanouts during netlist optimizations.
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "sw_a"
Info: Implemented 208 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 16 output pins
    Info: Implemented 187 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings
    Info: Peak virtual memory: 192 megabytes
    Info: Processing ended: Fri Dec 05 11:45:11 2008
    Info: Elapsed time: 00:00:05
    Info: Total CPU time (on all processors): 00:00:05