stopwatch.map.rpt

vhdl stopwatch -quartus2

; SDC constraint protection                                      ; Off                ; Off                ;
; Synthesis Effort                                               ; Auto               ; Auto               ;
; Allows Asynchronous Clear Usage For Shift Register Replacement ; On                 ; On                 ;
; Analysis & Synthesis Message Level                             ; Medium             ; Medium             ;
+----------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                               ;
+----------------------------------+-----------------+------------------------------+------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                     ;
+----------------------------------+-----------------+------------------------------+------------------------------------------------------------------+
; stopwatch.vhd                    ; yes             ; User VHDL File               ; D:/start/stopwach/stopwatch.vhd                                  ;
; lpm_divide.tdf                   ; yes             ; Megafunction                 ; c:/altera/81/quartus/libraries/megafunctions/lpm_divide.tdf      ;
; abs_divider.inc                  ; yes             ; Megafunction                 ; c:/altera/81/quartus/libraries/megafunctions/abs_divider.inc     ;
; sign_div_unsign.inc              ; yes             ; Megafunction                 ; c:/altera/81/quartus/libraries/megafunctions/sign_div_unsign.inc ;
; aglobal81.inc                    ; yes             ; Megafunction                 ; c:/altera/81/quartus/libraries/megafunctions/aglobal81.inc       ;
; db/lpm_divide_65m.tdf            ; yes             ; Auto-Generated Megafunction  ; D:/start/stopwach/db/lpm_divide_65m.tdf                          ;
; db/sign_div_unsign_dkh.tdf       ; yes             ; Auto-Generated Megafunction  ; D:/start/stopwach/db/sign_div_unsign_dkh.tdf                     ;
; db/alt_u_div_sve.tdf             ; yes             ; Auto-Generated Megafunction  ; D:/start/stopwach/db/alt_u_div_sve.tdf                           ;
; db/add_sub_lkc.tdf               ; yes             ; Auto-Generated Megafunction  ; D:/start/stopwach/db/add_sub_lkc.tdf                             ;
; db/add_sub_mkc.tdf               ; yes             ; Auto-Generated Megafunction  ; D:/start/stopwach/db/add_sub_mkc.tdf                             ;
; db/lpm_divide_0dm.tdf            ; yes             ; Auto-Generated Megafunction  ; D:/start/stopwach/db/lpm_divide_0dm.tdf                          ;
; db/sign_div_unsign_akh.tdf       ; yes             ; Auto-Generated Megafunction  ; D:/start/stopwach/db/sign_div_unsign_akh.tdf                     ;
; db/alt_u_div_mve.tdf             ; yes             ; Auto-Generated Megafunction  ; D:/start/stopwach/db/alt_u_div_mve.tdf                           ;
+----------------------------------+-----------------+------------------------------+------------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 178   ;
;                                             ;       ;
; Total combinational functions               ; 178   ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 74    ;
;     -- 3 input functions                    ; 33    ;
;     -- <=2 input functions                  ; 71    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 139   ;
;     -- arithmetic mode                      ; 39    ;
;                                             ;       ;
; Total registers                             ; 29    ;
;     -- Dedicated logic registers            ; 29    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 21    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 29    ;
; Total fan-out                               ; 637   ;
; Average fan-out                             ; 2.79  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                            ;
+----------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node             ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                        ; Library Name ;
+----------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------+--------------+
; |stopwatch                             ; 178 (80)          ; 29 (29)      ; 0           ; 0            ; 0       ; 0         ; 21   ; 0            ; |stopwatch                                                                                                 ; work         ;
;    |lpm_divide:Div0|                   ; 43 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|lpm_divide:Div0                                                                                 ; work         ;
;       |lpm_divide_0dm:auto_generated|  ; 43 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|lpm_divide:Div0|lpm_divide_0dm:auto_generated                                                   ; work         ;
;          |sign_div_unsign_akh:divider| ; 43 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|lpm_divide:Div0|lpm_divide_0dm:auto_generated|sign_div_unsign_akh:divider                       ; work         ;
;             |alt_u_div_mve:divider|    ; 43 (43)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|lpm_divide:Div0|lpm_divide_0dm:auto_generated|sign_div_unsign_akh:divider|alt_u_div_mve:divider ; work         ;
;    |lpm_divide:Mod0|                   ; 55 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|lpm_divide:Mod0                                                                                 ; work         ;
;       |lpm_divide_65m:auto_generated|  ; 55 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|lpm_divide:Mod0|lpm_divide_65m:auto_generated                                                   ; work         ;
;          |sign_div_unsign_dkh:divider| ; 55 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|lpm_divide:Mod0|lpm_divide_65m:auto_generated|sign_div_unsign_dkh:divider                       ; work         ;
;             |alt_u_div_sve:divider|    ; 55 (55)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|lpm_divide:Mod0|lpm_divide_65m:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_sve:divider ; work         ;
+----------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; break                                              ; GND                 ; yes                    ;
; Number of user-specified and inferred latches = 1  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; sw13                                  ; Stuck at VCC due to stuck port data_in ;
; sw12                                  ; Lost fanout                            ;
; sw11                                  ; Lost fanout                            ;
; Total Number of Removed Registers = 3 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                        ;
+---------------+---------------------------+----------------------------------------+
; Register name ; Reason for Removal        ; Registers Removed due to This Register ;
+---------------+---------------------------+----------------------------------------+
; sw13          ; Stuck at VCC              ; sw12, sw11                             ;
;               ; due to stuck port data_in ;                                        ;
+---------------+---------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 29    ;
; Number of registers using Synchronous Clear  ; 7     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 23    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 15    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; seg_com[4]~reg0                        ; 5       ;
; seg_com[6]~reg0                        ; 6       ;
; seg_com[0]~reg0                        ; 2       ;
; seg_com[3]~reg0                        ; 3       ;
; seg_com[1]~reg0                        ; 3       ;
; seg_com[2]~reg0                        ; 3       ;