stopwatch.vhd.bak

vhdl stopwatch -quartus2

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity stopwatch is
	port (	clk	: in bit;
			sw_d : in bit;
			seg : buffer std_logic_vector (7 downto 0);
			seg_com : buffer std_logic_vector (0 to 7);
			sw_a, sw_b , sw_c : in std_logic);
end stopwatch;

architecture arc of stopwatch is
	signal seg3, seg4 : std_logic_vector(7 downto 0);
	signal seg5, seg6 : std_logic_vector(7 downto 0);
	signal seg7, seg8 : std_logic_vector(7 downto 0);
	signal sec :integer range 0 to 9;
	signal msec :integer range 0 to 99;
	signal mmsec : integer range 0 to 9;
	signal cnt : integer range 0 to 999;
	signal sw11, sw12, sw13, sw21, sw22, sw23, sw31, sw32, sw33: std_logic;
	signal break : std_logic;
	

	function take (display : integer range 0 to 10)
	return std_logic_vector is
	variable seg_data : std_logic_vector(7 downto 0);
	begin
				case display is
					when 0 => seg_data := x"3f";
					when 1 => seg_data := x"06";
					when 2 => seg_data := x"5b";
					when 3 => seg_data := x"4f";
					when 4 => seg_data := x"66";
					when 5 => seg_data := x"6d";
					when 6 => seg_data := x"7d";
					when 7 => seg_data := x"27";
					when 8 => seg_data := x"7f";
					when 9 => seg_data := x"67";
					when others => seg_data := x"00";
				end case;
				return seg_data;
	end take;

	
	begin
	process(sw11, sw12, sw13)
	begin
		if clk='1' and clk'event then
			sw11<=sw_a;
			sw12<=sw11;
			if sw11='1' and sw12='0' then
				sw13<='1';
			else
				sw13<='0';
			end if;
		elsif clk='1' and clk'event then
			sw21<=sw_b;
			sw22<=sw21;
			if sw21='1' and sw22='0' then
				sw23<= '1';
			else
				sw23<='0';
			end if;
		elsif clk='1' and clk'event then
		
			sw31<=sw_c;
			sw32<=sw31;
			if sw31='1' and sw32='0' then
				sw33<='1';
			else
				sw33<='0';
			end if;
		end if;
	end process;

	process (sw_d, clk, cnt,  msec, sw_a, sec)
	begin
			
		if sw23='1' then
			break<= '1';
		elsif sw33='1' then
			break<='0';
		end if;
		if sw_d = '1' then
			sec <= 0;
			msec <= 0;
			mmsec<=0;
		elsif sw13='1' then
			if clk'event and clk='1' and break='0' then
				mmsec<=mmsec+1;
				if (mmsec>=9) then
					mmsec<=0;
					msec<=msec+1;
					if(msec>=99) then 
						msec<=0;
						sec<=sec+1;
						if(sec>=9) then
							sec<=0;
						end if;
					end if;
				end if;
			end if;
		
		end if;
						
	end process;
	
	
	
	

	
	process (sw_d, clk, seg_com, seg3, seg4, seg5, seg6, seg7, seg8)
	begin
		if sw_d='1' then
			seg_com(0 to 7) <= "11111110";
		elsif clk'event and clk='1' then
			if(seg_com="11110111") then
				seg_com(0 to 7)<="11111110";
			else
				seg_com(0 to 7) <= seg_com(1 to 7) & '1';
			end if;
		end if;
		case seg_com is
			when "11111110" =>seg(7 downto 0) <= seg8;
			when "11111101" =>seg(7 downto 0) <= seg7;
			when "11111011" =>seg(7 downto 0) <= seg6;
			when others =>seg(7 downto 0) <= seg5;
			
		end case;
	end process;
	
	seg5<=take(sec);
	seg6<=take(msec / 10);
	seg7<=take(msec mod 10);
	seg8<=take(mmsec);
	
end arc;