prev_cmp_stopwatch.qmsg

vhdl stopwatch -quartus2

{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "239 " "Info: Peak virtual memory: 239 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 05 11:43:41 2008 " "Info: Processing ended: Fri Dec 05 11:43:41 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:12 " "Info: Total CPU time (on all processors): 00:00:12" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Web Edition " "Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 05 11:43:42 2008 " "Info: Processing started: Fri Dec 05 11:43:42 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off stopwatch -c stopwatch " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off stopwatch -c stopwatch" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "216 " "Info: Peak virtual memory: 216 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 05 11:43:47 2008 " "Info: Processing ended: Fri Dec 05 11:43:47 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Info: Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Web Edition " "Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 05 11:43:48 2008 " "Info: Processing started: Fri Dec 05 11:43:48 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off stopwatch -c stopwatch --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off stopwatch -c stopwatch --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "break " "Warning: Node \"break\" is a latch" {  } { { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 23 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 7 -1 0 } } { "c:/altera/81/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/81/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register mmsec\[2\] register sec\[0\] 235.02 MHz 4.255 ns Internal " "Info: Clock \"clk\" has Internal fmax of 235.02 MHz between source register \"mmsec\[2\]\" and destination register \"sec\[0\]\" (period= 4.255 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.989 ns + Longest register register " "Info: + Longest register to register delay is 3.989 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mmsec\[2\] 1 REG LCFF_X35_Y9_N13 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X35_Y9_N13; Fanout = 11; REG Node = 'mmsec\[2\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { mmsec[2] } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.235 ns) + CELL(0.651 ns) 1.886 ns LessThan0~75 2 COMB LCCOMB_X34_Y9_N12 2 " "Info: 2: + IC(1.235 ns) + CELL(0.651 ns) = 1.886 ns; Loc. = LCCOMB_X34_Y9_N12; Fanout = 2; COMB Node = 'LessThan0~75'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.886 ns" { mmsec[2] LessThan0~75 } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 93 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.419 ns) + CELL(0.499 ns) 2.804 ns sec\[3\]~211 3 COMB LCCOMB_X34_Y9_N14 4 " "Info: 3: + IC(0.419 ns) + CELL(0.499 ns) = 2.804 ns; Loc. = LCCOMB_X34_Y9_N14; Fanout = 4; COMB Node = 'sec\[3\]~211'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.918 ns" { LessThan0~75 sec[3]~211 } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.330 ns) + CELL(0.855 ns) 3.989 ns sec\[0\] 4 REG LCFF_X34_Y9_N17 11 " "Info: 4: + IC(0.330 ns) + CELL(0.855 ns) = 3.989 ns; Loc. = LCFF_X34_Y9_N17; Fanout = 11; REG Node = 'sec\[0\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.185 ns" { sec[3]~211 sec[0] } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.005 ns ( 50.26 % ) " "Info: Total cell delay = 2.005 ns ( 50.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.984 ns ( 49.74 % ) " "Info: Total interconnect delay = 1.984 ns ( 49.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.989 ns" { mmsec[2] LessThan0~75 sec[3]~211 sec[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.989 ns" { mmsec[2] {} LessThan0~75 {} sec[3]~211 {} sec[0] {} } { 0.000ns 1.235ns 0.419ns 0.330ns } { 0.000ns 0.651ns 0.499ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.002 ns - Smallest " "Info: - Smallest clock skew is -0.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.165 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.165 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns clk 1 CLK PIN_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.232 ns) + CELL(0.000 ns) 1.342 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.232 ns) + CELL(0.000 ns) = 1.342 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.232 ns" { clk clk~clkctrl } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.157 ns) + CELL(0.666 ns) 3.165 ns sec\[0\] 3 REG LCFF_X34_Y9_N17 11 " "Info: 3: + IC(1.157 ns) + CELL(0.666 ns) = 3.165 ns; Loc. = LCFF_X34_Y9_N17; Fanout = 11; REG Node = 'sec\[0\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.823 ns" { clk~clkctrl sec[0] } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.776 ns ( 56.11 % ) " "Info: Total cell delay = 1.776 ns ( 56.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.389 ns ( 43.89 % ) " "Info: Total interconnect delay = 1.389 ns ( 43.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.165 ns" { clk clk~clkctrl sec[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.165 ns" { clk {} clk~combout {} clk~clkctrl {} sec[0] {} } { 0.000ns 0.000ns 0.232ns 1.157ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.167 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.167 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns clk 1 CLK PIN_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.232 ns) + CELL(0.000 ns) 1.342 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.232 ns) + CELL(0.000 ns) = 1.342 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.232 ns" { clk clk~clkctrl } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.159 ns) + CELL(0.666 ns) 3.167 ns mmsec\[2\] 3 REG LCFF_X35_Y9_N13 11 " "Info: 3: + IC(1.159 ns) + CELL(0.666 ns) = 3.167 ns; Loc. = LCFF_X35_Y9_N13; Fanout = 11; REG Node = 'mmsec\[2\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.825 ns" { clk~clkctrl mmsec[2] } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.776 ns ( 56.08 % ) " "Info: Total cell delay = 1.776 ns ( 56.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.391 ns ( 43.92 % ) " "Info: Total interconnect delay = 1.391 ns ( 43.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.167 ns" { clk clk~clkctrl mmsec[2] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.167 ns" { clk {} clk~combout {} clk~clkctrl {} mmsec[2] {} } { 0.000ns 0.000ns 0.232ns 1.159ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.165 ns" { clk clk~clkctrl sec[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.165 ns" { clk {} clk~combout {} clk~clkctrl {} sec[0] {} } { 0.000ns 0.000ns 0.232ns 1.157ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.167 ns" { clk clk~clkctrl mmsec[2] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.167 ns" { clk {} clk~combout {} clk~clkctrl {} mmsec[2] {} } { 0.000ns 0.000ns 0.232ns 1.159ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 91 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 91 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.989 ns" { mmsec[2] LessThan0~75 sec[3]~211 sec[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.989 ns" { mmsec[2] {} LessThan0~75 {} sec[3]~211 {} sec[0] {} } { 0.000ns 1.235ns 0.419ns 0.330ns } { 0.000ns 0.651ns 0.499ns 0.855ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.165 ns" { clk clk~clkctrl sec[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.165 ns" { clk {} clk~combout {} clk~clkctrl {} sec[0] {} } { 0.000ns 0.000ns 0.232ns 1.157ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.167 ns" { clk clk~clkctrl mmsec[2] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.167 ns" { clk {} clk~combout {} clk~clkctrl {} mmsec[2] {} } { 0.000ns 0.000ns 0.232ns 1.159ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "sw11 sw_a clk 5.618 ns register " "Info: tsu for register \"sw11\" (data pin = \"sw_a\", clock pin = \"clk\") is 5.618 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.825 ns + Longest pin register " "Info: + Longest pin to register delay is 8.825 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.914 ns) 0.914 ns sw_a 1 PIN PIN_Y10 1 " "Info: 1: + IC(0.000 ns) + CELL(0.914 ns) = 0.914 ns; Loc. = PIN_Y10; Fanout = 1; PIN Node = 'sw_a'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { sw_a } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.451 ns) + CELL(0.460 ns) 8.825 ns sw11 2 REG LCFF_X35_Y9_N5 2 " "Info: 2: + IC(7.451 ns) + CELL(0.460 ns) = 8.825 ns; Loc. = LCFF_X35_Y9_N5; Fanout = 2; REG Node = 'sw11'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.911 ns" { sw_a sw11 } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.374 ns ( 15.57 % ) " "Info: Total cell delay = 1.374 ns ( 15.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.451 ns ( 84.43 % ) " "Info: Total interconnect delay = 7.451 ns ( 84.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "8.825 ns" { sw_a sw11 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "8.825 ns" { sw_a {} sw_a~combout {} sw11 {} } { 0.000ns 0.000ns 7.451ns } { 0.000ns 0.914ns 0.460ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.167 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.167 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns clk 1 CLK PIN_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.232 ns) + CELL(0.000 ns) 1.342 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.232 ns) + CELL(0.000 ns) = 1.342 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.232 ns" { clk clk~clkctrl } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.159 ns) + CELL(0.666 ns) 3.167 ns sw11 3 REG LCFF_X35_Y9_N5 2 " "Info: 3: + IC(1.159 ns) + CELL(0.666 ns) = 3.167 ns; Loc. = LCFF_X35_Y9_N5; Fanout = 2; REG Node = 'sw11'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.825 ns" { clk~clkctrl sw11 } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.776 ns ( 56.08 % ) " "Info: Total cell delay = 1.776 ns ( 56.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.391 ns ( 43.92 % ) " "Info: Total interconnect delay = 1.391 ns ( 43.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.167 ns" { clk clk~clkctrl sw11 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.167 ns" { clk {} clk~combout {} clk~clkctrl {} sw11 {} } { 0.000ns 0.000ns 0.232ns 1.159ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "8.825 ns" { sw_a sw11 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "8.825 ns" { sw_a {} sw_a~combout {} sw11 {} } { 0.000ns 0.000ns 7.451ns } { 0.000ns 0.914ns 0.460ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.167 ns" { clk clk~clkctrl sw11 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.167 ns" { clk {} clk~combout {} clk~clkctrl {} sw11 {} } { 0.000ns 0.000ns 0.232ns 1.159ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg\[6\] msec\[4\] 31.532 ns register " "Info: tco from clock \"clk\" to destination pin \"seg\[6\]\" through register \"msec\[4\]\" is 31.532 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.165 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.165 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns clk 1 CLK PIN_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.232 ns) + CELL(0.000 ns) 1.342 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.232 ns) + CELL(0.000 ns) = 1.342 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.232 ns" { clk clk~clkctrl } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.157 ns) + CELL(0.666 ns) 3.165 ns msec\[4\] 3 REG LCFF_X34_Y9_N27 11 " "Info: 3: + IC(1.157 ns) + CELL(0.666 ns) = 3.165 ns; Loc. = LCFF_X34_Y9_N27; Fanout = 11; REG Node = 'msec\[4\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.823 ns" { clk~clkctrl msec[4] } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.776 ns ( 56.11 % ) " "Info: Total cell delay = 1.776 ns ( 56.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.389 ns ( 43.89 % ) " "Info: Total interconnect delay = 1.389 ns ( 43.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.165 ns" { clk clk~clkctrl msec[4] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.165 ns" { clk {} clk~combout {} clk~clkctrl {} msec[4] {} } { 0.000ns 0.000ns 0.232ns 1.157ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 91 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "28.063 ns + Longest register pin " "Info: + Longest register to pin delay is 28.063 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns msec\[4\] 1 REG