📄 sign_div_unsign_dkh.tdf
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--sign_div_unsign DEN_REPRESENTATION="UNSIGNED" DEN_WIDTH=7 LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="UNSIGNED" NUM_WIDTH=7 SKIP_BITS=0 denominator numerator quotient remainder
--VERSION_BEGIN 8.1 cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_abs 2008:05:19:10:51:43:SJ cbx_lpm_add_sub 2008:05:19:10:49:01:SJ cbx_lpm_divide 2008:05:21:18:11:28:SJ cbx_mgl 2008:08:08:15:16:18:SJ cbx_stratix 2008:08:05:17:10:23:SJ cbx_stratixii 2008:08:07:13:54:47:SJ cbx_util_mgl 2008:07:18:09:58:54:SJ VERSION_END
-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
FUNCTION alt_u_div_sve (denominator[6..0], numerator[6..0])
RETURNS ( quotient[6..0], remainder[6..0]);
--synthesis_resources = lut 30
SUBDESIGN sign_div_unsign_dkh
(
denominator[6..0] : input;
numerator[6..0] : input;
quotient[6..0] : output;
remainder[6..0] : output;
)
VARIABLE
divider : alt_u_div_sve;
norm_num[6..0] : WIRE;
protect_quotient[6..0] : WIRE;
protect_remainder[6..0] : WIRE;
BEGIN
divider.denominator[] = denominator[];
divider.numerator[] = norm_num[];
norm_num[] = numerator[];
protect_quotient[] = divider.quotient[];
protect_remainder[] = divider.remainder[];
quotient[] = protect_quotient[];
remainder[] = protect_remainder[];
END;
--VALID FILE
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