stopwatch.tan.qmsg

vhdl stopwatch -quartus2

{ "Info" "ITDB_TH_RESULT" "sw21 sw_b clk -4.851 ns register " "Info: th for register \"sw21\" (data pin = \"sw_b\", clock pin = \"clk\") is -4.851 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.190 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.190 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns clk 1 CLK PIN_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.232 ns) + CELL(0.000 ns) 1.342 ns clk~clkctrl 2 COMB CLKCTRL_G2 29 " "Info: 2: + IC(0.232 ns) + CELL(0.000 ns) = 1.342 ns; Loc. = CLKCTRL_G2; Fanout = 29; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.232 ns" { clk clk~clkctrl } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.182 ns) + CELL(0.666 ns) 3.190 ns sw21 3 REG LCFF_X30_Y11_N11 2 " "Info: 3: + IC(1.182 ns) + CELL(0.666 ns) = 3.190 ns; Loc. = LCFF_X30_Y11_N11; Fanout = 2; REG Node = 'sw21'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.848 ns" { clk~clkctrl sw21 } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.776 ns ( 55.67 % ) " "Info: Total cell delay = 1.776 ns ( 55.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.414 ns ( 44.33 % ) " "Info: Total interconnect delay = 1.414 ns ( 44.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.190 ns" { clk clk~clkctrl sw21 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.190 ns" { clk {} clk~combout {} clk~clkctrl {} sw21 {} } { 0.000ns 0.000ns 0.232ns 1.182ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.347 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.347 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.914 ns) 0.914 ns sw_b 1 PIN PIN_W10 1 " "Info: 1: + IC(0.000 ns) + CELL(0.914 ns) = 0.914 ns; Loc. = PIN_W10; Fanout = 1; PIN Node = 'sw_b'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { sw_b } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.973 ns) + CELL(0.460 ns) 8.347 ns sw21 2 REG LCFF_X30_Y11_N11 2 " "Info: 2: + IC(6.973 ns) + CELL(0.460 ns) = 8.347 ns; Loc. = LCFF_X30_Y11_N1