stopwatch.tan.qmsg

vhdl stopwatch -quartus2

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 7 -1 0 } } { "c:/altera/81/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/81/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register msec\[4\] register sec\[0\] 255.3 MHz 3.917 ns Internal " "Info: Clock \"clk\" has Internal fmax of 255.3 MHz between source register \"msec\[4\]\" and destination register \"sec\[0\]\" (period= 3.917 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.653 ns + Longest register register " "Info: + Longest register to register delay is 3.653 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns msec\[4\] 1 REG LCFF_X31_Y11_N27 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y11_N27; Fanout = 11; REG Node = 'msec\[4\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { msec[4] } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.784 ns) + CELL(0.535 ns) 1.319 ns LessThan1~118 2 COMB LCCOMB_X31_Y11_N0 1 " "Info: 2: + IC(0.784 ns) + CELL(0.535 ns) = 1.319 ns; Loc. = LCCOMB_X31_Y11_N0; Fanout = 1; COMB Node = 'LessThan1~118'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.319 ns" { msec[4] LessThan1~118 } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 95 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.362 ns) + CELL(0.206 ns) 1.887 ns LessThan1~119 3 COMB LCCOMB_X31_Y11_N2 8 " "Info: 3: + IC(0.362 ns) + CELL(0.206 ns) = 1.887 ns; Loc. = LCCOMB_X31_Y11_N2; Fanout = 8; COMB Node = 'LessThan1~119'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.568 ns" { LessThan1~118 LessThan1~119 } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 95 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.375 ns) + CELL(0.206 ns) 2.468 ns sec\[3\]~208 4 COMB LCCOMB_X31_Y11_N14 4 " "Info: 4: + IC(0.375 ns) + CELL(0.206 ns) = 2.468 ns; Loc. = LCCOMB_X31_Y11_N14; Fanout = 4; COMB Node = 'sec\[3\]~208'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.581 ns" { LessThan1~119 sec[3]~208 } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.330 ns) + CELL(0.855 ns) 3.653 ns sec\[0\] 5 REG LCFF_X31_Y11_N17 11 " "Info: 5: + IC(0.330 ns) + CELL(0.855 ns) = 3.653 ns; Loc. = LCFF_X31_Y11_N17; Fanout = 11; REG Node = 'sec\[0\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.185 ns" { sec[3]~208 sec[0] } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.802 ns ( 49.33 % ) " "Info: Total cell delay = 1.802 ns ( 49.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.851 ns ( 50.67 % ) " "Info: Total interconnect delay = 1.851 ns ( 50.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.653 ns" { msec[4] LessThan1~118 LessThan1~119 sec[3]~208 sec[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.653 ns" { msec[4] {} LessThan1~118 {} LessThan1~119 {} sec[3]~208 {} sec[0] {} } { 0.000ns 0.784ns 0.362ns 0.375ns 0.330ns } { 0.000ns 0.535ns 0.206ns 0.206ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.190 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.190 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns clk 1 CLK PIN_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.232 ns) + CELL(0.000 ns) 1.342 ns clk~clkctrl 2 COMB CLKCTRL_G2 29 " "Info: 2: + IC(0.232 ns) + CELL(0.000 ns) = 1.342 ns; Loc. = CLKCTRL_G2; Fanout = 29; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.232 ns" { clk clk~clkctrl } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.182 ns) + CELL(0.666 ns) 3.190 ns sec\[0\] 3 REG LCFF_X31_Y11_N17 11 " "Info: 3: + IC(1.182 ns) + CELL(0.666 ns) = 3.190 ns; Loc. = LCFF_X31_Y11_N17; Fanout = 11; REG Node = 'sec\[0\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.848 ns" { clk~clkctrl sec[0] } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.776 ns ( 55.67 % ) " "Info: Total cell delay = 1.776 ns ( 55.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.414 ns ( 44.33 % ) " "Info: Total interconnect delay = 1.414 ns ( 44.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.190 ns" { clk clk~clkctrl sec[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.190 ns" { clk {} clk~combout {} clk~clkctrl {} sec[0] {} } { 0.000ns 0.000ns 0.232ns 1.182ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.190 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.190 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns clk 1 CLK PIN_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.232 ns) + CELL(0.000 ns) 1.342 ns clk~clkctrl 2 COMB CLKCTRL_G2 29 " "Info: 2: + IC(0.232 ns) + CELL(0.000 ns) = 1.342 ns; Loc. = CLKCTRL_G2; Fanout = 29; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.232 ns" { clk clk~clkctrl } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.182 ns) + CELL(0.666 ns) 3.190 ns msec\[4\] 3 REG LCFF_X31_Y11_N27 11 " "Info: 3: + IC(1.182 ns) + CELL(0.666 ns) = 3.190 ns; Loc. = LCFF_X31_Y11_N27; Fanout = 11; REG Node = 'msec\[4\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.848 ns" { clk~clkctrl msec[4] } "NODE_NAME" } } { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.776 ns ( 55.67 % ) " "Info: Total cell delay = 1.776 ns ( 55.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.414 ns ( 44.33 % ) " "Info: Total interconnect delay = 1.414 ns ( 44.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.190 ns" { clk clk~clkctrl msec[4] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.190 ns" { clk {} clk~combout {} clk~clkctrl {} msec[4] {} } { 0.000ns 0.000ns 0.232ns 1.182ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.190 ns" { clk clk~clkctrl sec[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.190 ns" { clk {} clk~combout {} clk~clkctrl {} sec[0] {} } { 0.000ns 0.000ns 0.232ns 1.182ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.190 ns" { clk clk~clkctrl msec[4] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.190 ns" { clk {} clk~combout {} clk~clkctrl {} msec[4] {} } { 0.000ns 0.000ns 0.232ns 1.182ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 90 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 90 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.653 ns" { msec[4] LessThan1~118 LessThan1~119 sec[3]~208 sec[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.653 ns" { msec[4] {} LessThan1~118 {} LessThan1~119 {} sec[3]~208 {} sec[0] {} } { 0.000ns 0.784ns 0.362ns 0.375ns 0.330ns } { 0.000ns 0.535ns 0.206ns 0.206ns 0.855ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.190 ns" { clk clk~clkctrl sec[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.190 ns" { clk {} clk~combout {} clk~clkctrl {} sec[0] {} } { 0.000ns 0.000ns 0.232ns 1.182ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.190 ns" { clk clk~clkctrl msec[4] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.190 ns" { clk {} clk~combout {} clk~clkctrl {} msec[4] {} } { 0.000ns 0.000ns 0.232ns 1.182ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}