stopwatch.map.qmsg

vhdl stopwatch -quartus2

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_dkh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_dkh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_dkh " "Info: Found entity 1: sign_div_unsign_dkh" {  } { { "db/sign_div_unsign_dkh.tdf" "" { Text "D:/start/stopwach/db/sign_div_unsign_dkh.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_sve.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_sve.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_sve " "Info: Found entity 1: alt_u_div_sve" {  } { { "db/alt_u_div_sve.tdf" "" { Text "D:/start/stopwach/db/alt_u_div_sve.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_lkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_lkc " "Info: Found entity 1: add_sub_lkc" {  } { { "db/add_sub_lkc.tdf" "" { Text "D:/start/stopwach/db/add_sub_lkc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_mkc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_mkc " "Info: Found entity 1: add_sub_mkc" {  } { { "db/add_sub_mkc.tdf" "" { Text "D:/start/stopwach/db/add_sub_mkc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_divide:Div0 " "Info: Elaborated megafunction instantiation \"lpm_divide:Div0\"" {  } { { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 135 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_divide:Div0 " "Info: Instantiated megafunction \"lpm_divide:Div0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 7 " "Info: Parameter \"LPM_WIDTHN\" = \"7\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Info: Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Info: Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Info: Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } { { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 135 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_0dm.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_0dm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_0dm " "Info: Found entity 1: lpm_divide_0dm" {  } { { "db/lpm_divide_0dm.tdf" "" { Text "D:/start/stopwach/db/lpm_divide_0dm.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_akh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_akh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_akh " "Info: Found entity 1: sign_div_unsign_akh" {  } { { "db/sign_div_unsign_akh.tdf" "" { Text "D:/start/stopwach/db/sign_div_unsign_akh.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_mve.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_mve.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_mve " "Info: Found entity 1: alt_u_div_mve" {  } { { "db/alt_u_div_mve.tdf" "" { Text "D:/start/stopwach/db/alt_u_div_mve.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 116 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "seg\[7\] GND " "Warning (13410): Pin \"seg\[7\]\" is stuck at GND" {  } { { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 9 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 2 " "Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sw12 " "Info: Register \"sw12\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sw11 " "Info: Register \"sw11\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "sw_a " "Warning (15610): No output dependent on input pin \"sw_a\"" {  } { { "stopwatch.vhd" "" { Text "D:/start/stopwach/stopwatch.vhd" 11 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "208 " "Info: Implemented 208 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "187 " "Info: Implemented 187 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "192 " "Info: Peak virtual memory: 192 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 05 11:45:11 2008 " "Info: Processing ended: Fri Dec 05 11:45:11 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Info: Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}