stopwatch.tan.rpt

vhdl stopwatch -quartus2

; N/A   ; None         ; 13.549 ns  ; mmsec[2]        ; seg[5]     ; clk        ;
; N/A   ; None         ; 13.538 ns  ; mmsec[1]        ; seg[5]     ; clk        ;
; N/A   ; None         ; 13.423 ns  ; mmsec[2]        ; seg[4]     ; clk        ;
; N/A   ; None         ; 13.319 ns  ; mmsec[1]        ; seg[1]     ; clk        ;
; N/A   ; None         ; 13.302 ns  ; mmsec[0]        ; seg[1]     ; clk        ;
; N/A   ; None         ; 13.260 ns  ; mmsec[3]        ; seg[0]     ; clk        ;
; N/A   ; None         ; 13.135 ns  ; seg_com[7]~reg0 ; seg[5]     ; clk        ;
; N/A   ; None         ; 13.116 ns  ; mmsec[3]        ; seg[5]     ; clk        ;
; N/A   ; None         ; 13.084 ns  ; mmsec[0]        ; seg[0]     ; clk        ;
; N/A   ; None         ; 13.023 ns  ; mmsec[3]        ; seg[4]     ; clk        ;
; N/A   ; None         ; 12.907 ns  ; mmsec[2]        ; seg[1]     ; clk        ;
; N/A   ; None         ; 12.884 ns  ; seg_com[7]~reg0 ; seg[4]     ; clk        ;
; N/A   ; None         ; 12.852 ns  ; sec[1]          ; seg[5]     ; clk        ;
; N/A   ; None         ; 12.803 ns  ; sec[0]          ; seg[5]     ; clk        ;
; N/A   ; None         ; 12.776 ns  ; sec[1]          ; seg[1]     ; clk        ;
; N/A   ; None         ; 12.724 ns  ; sec[0]          ; seg[1]     ; clk        ;
; N/A   ; None         ; 12.643 ns  ; seg_com[7]~reg0 ; seg[1]     ; clk        ;
; N/A   ; None         ; 12.567 ns  ; sec[3]          ; seg[5]     ; clk        ;
; N/A   ; None         ; 12.513 ns  ; mmsec[3]        ; seg[1]     ; clk        ;
; N/A   ; None         ; 12.495 ns  ; sec[3]          ; seg[1]     ; clk        ;
; N/A   ; None         ; 12.422 ns  ; sec[2]          ; seg[5]     ; clk        ;
; N/A   ; None         ; 12.355 ns  ; sec[2]          ; seg[1]     ; clk        ;
; N/A   ; None         ; 12.350 ns  ; sec[2]          ; seg[0]     ; clk        ;
; N/A   ; None         ; 12.299 ns  ; sec[0]          ; seg[0]     ; clk        ;
; N/A   ; None         ; 12.068 ns  ; sec[1]          ; seg[0]     ; clk        ;
; N/A   ; None         ; 12.065 ns  ; msec[0]         ; seg[5]     ; clk        ;
; N/A   ; None         ; 11.908 ns  ; msec[0]         ; seg[1]     ; clk        ;
; N/A   ; None         ; 11.877 ns  ; sec[3]          ; seg[0]     ; clk        ;
; N/A   ; None         ; 11.773 ns  ; sec[1]          ; seg[4]     ; clk        ;
; N/A   ; None         ; 11.714 ns  ; sec[0]          ; seg[4]     ; clk        ;
; N/A   ; None         ; 11.493 ns  ; sec[3]          ; seg[4]     ; clk        ;
; N/A   ; None         ; 11.349 ns  ; sec[2]          ; seg[4]     ; clk        ;
; N/A   ; None         ; 11.227 ns  ; seg_com[7]~reg0 ; seg_com[7] ; clk        ;
; N/A   ; None         ; 10.905 ns  ; seg_com[4]~reg0 ; seg_com[4] ; clk        ;
; N/A   ; None         ; 10.515 ns  ; seg_com[3]~reg0 ; seg_com[3] ; clk        ;
; N/A   ; None         ; 10.191 ns  ; seg_com[6]~reg0 ; seg_com[6] ; clk        ;
; N/A   ; None         ; 10.178 ns  ; seg_com[5]~reg0 ; seg_com[5] ; clk        ;
; N/A   ; None         ; 9.704 ns   ; seg_com[1]~reg0 ; seg_com[1] ; clk        ;
; N/A   ; None         ; 9.261 ns   ; seg_com[2]~reg0 ; seg_com[2] ; clk        ;
; N/A   ; None         ; 9.064 ns   ; seg_com[0]~reg0 ; seg_com[0] ; clk        ;
+-------+--------------+------------+-----------------+------------+------------+


+------------------------------------------------------------------+
; th                                                               ;
+---------------+-------------+-----------+------+------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To   ; To Clock ;
+---------------+-------------+-----------+------+------+----------+
; N/A           ; None        ; -4.851 ns ; sw_b ; sw21 ; clk      ;
; N/A           ; None        ; -4.892 ns ; sw_c ; sw31 ; clk      ;
+---------------+-------------+-----------+------+------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition
    Info: Processing started: Fri Dec 05 11:45:31 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off stopwatch -c stopwatch --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "break" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 255.3 MHz between source register "msec[4]" and destination register "sec[0]" (period= 3.917 ns)
    Info: + Longest register to register delay is 3.653 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y11_N27; Fanout = 11; REG Node = 'msec[4]'
        Info: 2: + IC(0.784 ns) + CELL(0.535 ns) = 1.319 ns; Loc. = LCCOMB_X31_Y11_N0; Fanout = 1; COMB Node = 'LessThan1~118'
        Info: 3: + IC(0.362 ns) + CELL(0.206 ns) = 1.887 ns; Loc. = LCCOMB_X31_Y11_N2; Fanout = 8; COMB Node = 'LessThan1~119'
        Info: 4: + IC(0.375 ns) + CELL(0.206 ns) = 2.468 ns; Loc. = LCCOMB_X31_Y11_N14; Fanout = 4; COMB Node = 'sec[3]~208'
        Info: 5: + IC(0.330 ns) + CELL(0.855 ns) = 3.653 ns; Loc. = LCFF_X31_Y11_N17; Fanout = 11; REG Node = 'sec[0]'
        Info: Total cell delay = 1.802 ns ( 49.33 % )
        Info: Total interconnect delay = 1.851 ns ( 50.67 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.190 ns
            Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.232 ns) + CELL(0.000 ns) = 1.342 ns; Loc. = CLKCTRL_G2; Fanout = 29; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(1.182 ns) + CELL(0.666 ns) = 3.190 ns; Loc. = LCFF_X31_Y11_N17; Fanout = 11; REG Node = 'sec[0]'
            Info: Total cell delay = 1.776 ns ( 55.67 % )
            Info: Total interconnect delay = 1.414 ns ( 44.33 % )
        Info: - Longest clock path from clock "clk" to source register is 3.190 ns
            Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.232 ns) + CELL(0.000 ns) = 1.342 ns; Loc. = CLKCTRL_G2; Fanout = 29; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(1.182 ns) + CELL(0.666 ns) = 3.190 ns; Loc. = LCFF_X31_Y11_N27; Fanout = 11; REG Node = 'msec[4]'
            Info: Total cell delay = 1.776 ns ( 55.67 % )
            Info: Total interconnect delay = 1.414 ns ( 44.33 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "sw31" (data pin = "sw_c", clock pin = "clk") is 5.158 ns
    Info: + Longest pin to register delay is 8.388 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_AA9; Fanout = 1; PIN Node = 'sw_c'
        Info: 2: + IC(6.994 ns) + CELL(0.460 ns) = 8.388 ns; Loc. = LCFF_X30_Y11_N7; Fanout = 2; REG Node = 'sw31'
        Info: Total cell delay = 1.394 ns ( 16.62 % )
        Info: Total interconnect delay = 6.994 ns ( 83.38 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.190 ns
        Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.232 ns) + CELL(0.000 ns) = 1.342 ns; Loc. = CLKCTRL_G2; Fanout = 29; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.182 ns) + CELL(0.666 ns) = 3.190 ns; Loc. = LCFF_X30_Y11_N7; Fanout = 2; REG Node = 'sw31'
        Info: Total cell delay = 1.776 ns ( 55.67 % )
        Info: Total interconnect delay = 1.414 ns ( 44.33 % )
Info: tco from clock "clk" to destination pin "seg[3]" through register "msec[4]" is 30.096 ns
    Info: + Longest clock path from clock "clk" to source register is 3.190 ns
        Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.232 ns) + CELL(0.000 ns) = 1.342 ns; Loc. = CL