stopwatch.sim.rpt

vhdl stopwatch -quartus2

; Display missing 0-value coverage report                                                    ; On         ; On            ;
; Detect setup and hold time violations                                                      ; Off        ; Off           ;
; Detect glitches                                                                            ; Off        ; Off           ;
; Disable timing delays in Timing Simulation                                                 ; Off        ; Off           ;
; Generate Signal Activity File                                                              ; Off        ; Off           ;
; Generate VCD File for PowerPlay Power Analyzer                                             ; Off        ; Off           ;
; Group bus channels in simulation results                                                   ; Off        ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements                            ; On         ; On            ;
; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off        ; Off           ;
; Overwrite Waveform Inputs With Simulation Outputs                                          ; Off        ;               ;
; Perform Glitch Filtering in Timing Simulation                                              ; Auto       ; Auto          ;
+--------------------------------------------------------------------------------------------+------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      12.96 % ;
; Total nodes checked                                 ; 240          ;
; Total output ports checked                          ; 270          ;
; Total output ports with complete 1/0-value coverage ; 35           ;
; Total output ports with no 1/0-value coverage       ; 231          ;
; Total output ports with no 1-value coverage         ; 231          ;
; Total output ports with no 0-value coverage         ; 235          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+----------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                ;
+----------------------------+----------------------------+------------------+
; Node Name                  ; Output Port Name           ; Output Port Type ;
+----------------------------+----------------------------+------------------+
; |stopwatch|seg_com[4]~reg0 ; |stopwatch|seg_com[4]~reg0 ; regout           ;
; |stopwatch|seg_com[6]~reg0 ; |stopwatch|seg_com[6]~reg0 ; regout           ;
; |stopwatch|seg_com[7]~reg0 ; |stopwatch|seg_com[7]~reg0 ; regout           ;
; |stopwatch|seg_com[5]~reg0 ; |stopwatch|seg_com[5]~reg0 ; regout           ;
; |stopwatch|Equal0~61       ; |stopwatch|Equal0~61       ; combout          ;
; |stopwatch|Mux6~603        ; |stopwatch|Mux6~603        ; combout          ;
; |stopwatch|Mux6~604        ; |stopwatch|Mux6~604        ; combout          ;
; |stopwatch|Mux6~605        ; |stopwatch|Mux6~605        ; combout          ;
; |stopwatch|Mux6~606        ; |stopwatch|Mux6~606        ; combout          ;
; |stopwatch|Mux6~607        ; |stopwatch|Mux6~607        ; combout          ;
; |stopwatch|Mux5~263        ; |stopwatch|Mux5~263        ; combout          ;
; |stopwatch|Mux5~264        ; |stopwatch|Mux5~264        ; combout          ;
; |stopwatch|Mux4~263        ; |stopwatch|Mux4~263        ; combout          ;
; |stopwatch|Mux4~264        ; |stopwatch|Mux4~264        ; combout          ;
; |stopwatch|Mux3~263        ; |stopwatch|Mux3~263        ; combout          ;
; |stopwatch|Mux3~264        ; |stopwatch|Mux3~264        ; combout          ;
; |stopwatch|Mux2~263        ; |stopwatch|Mux2~263        ; combout          ;
; |stopwatch|Mux2~264        ; |stopwatch|Mux2~264        ; combout          ;
; |stopwatch|Mux1~263        ; |stopwatch|Mux1~263        ; combout          ;
; |stopwatch|Mux0~263        ; |stopwatch|Mux0~263        ; combout          ;
; |stopwatch|Equal0~62       ; |stopwatch|Equal0~62       ; combout          ;
; |stopwatch|sw23            ; |stopwatch|sw23            ; regout           ;
; |stopwatch|process0~1      ; |stopwatch|process0~1      ; combout          ;
; |stopwatch|seg_com[6]~73   ; |stopwatch|seg_com[6]~73   ; combout          ;
; |stopwatch|seg[0]          ; |stopwatch|seg[0]          ; padio            ;
; |stopwatch|seg[1]          ; |stopwatch|seg[1]          ; padio            ;