swatch.map.rpt

swatch - quartus2 vhdl

Warning (10492): VHDL Process Statement warning at swatch.vhd(123): signal "sw23" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at swatch.vhd(132): signal "mode" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at swatch.vhd(133): signal "hourp" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at swatch.vhd(134): signal "hourp" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at swatch.vhd(137): signal "mode" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at swatch.vhd(138): signal "minp" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at swatch.vhd(139): signal "minp" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at swatch.vhd(142): signal "mode" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at swatch.vhd(143): signal "secp" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at swatch.vhd(144): signal "secp" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at swatch.vhd(151): signal "mode" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at swatch.vhd(152): signal "hourp" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at swatch.vhd(153): signal "hourp" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at swatch.vhd(156): signal "mode" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at swatch.vhd(157): signal "minp" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at swatch.vhd(158): signal "minp" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at swatch.vhd(161): signal "mode" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at swatch.vhd(162): signal "secp" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at swatch.vhd(163): signal "secp" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at swatch.vhd(129): inferring latch(es) for signal or variable "hourp", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at swatch.vhd(129): inferring latch(es) for signal or variable "minp", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at swatch.vhd(129): inferring latch(es) for signal or variable "secp", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "secp[0]" at swatch.vhd(129)
Info (10041): Inferred latch for "secp[1]" at swatch.vhd(129)
Info (10041): Inferred latch for "secp[2]" at swatch.vhd(129)
Info (10041): Inferred latch for "secp[3]" at swatch.vhd(129)
Info (10041): Inferred latch for "secp[4]" at swatch.vhd(129)
Info (10041): Inferred latch for "secp[5]" at swatch.vhd(129)
Info (10041): Inferred latch for "minp[0]" at swatch.vhd(129)
Info (10041): Inferred latch for "minp[1]" at swatch.vhd(129)
Info (10041): Inferred latch for "minp[2]" at swatch.vhd(129)
Info (10041): Inferred latch for "minp[3]" at swatch.vhd(129)
Info (10041): Inferred latch for "minp[4]" at swatch.vhd(129)
Info (10041): Inferred latch for "minp[5]" at swatch.vhd(129)
Info (10041): Inferred latch for "hourp[0]" at swatch.vhd(129)
Info (10041): Inferred latch for "hourp[1]" at swatch.vhd(129)
Info (10041): Inferred latch for "hourp[2]" at swatch.vhd(129)
Info (10041): Inferred latch for "hourp[3]" at swatch.vhd(129)
Info (10041): Inferred latch for "hourp[4]" at swatch.vhd(129)
Info (10041): Inferred latch for "mode[2]" at swatch.vhd(70)
Info (10041): Inferred latch for "mode[1]" at swatch.vhd(70)
Info (10041): Inferred latch for "mode[0]" at swatch.vhd(70)
Warning (14130): Reduced register "dot[0]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "dot[1]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "dot[2]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "dot[3]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "dot[4]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "dot[5]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "dot[6]" with stuck data_in port to stuck value GND
Info: Inferred 6 megafunctions from design logic
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Div0"
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Mod2"
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Mod1"
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Div1"
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Div2"
    Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Mod0"
Info: Elaborated megafunction instantiation "lpm_divide:Div0"
Info: Instantiated megafunction "lpm_divide:Div0" with the following parameter:
    Info: Parameter "LPM_WIDTHN" = "5"
    Info: Parameter "LPM_WIDTHD" = "4"
    Info: Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
    Info: Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_ucm.tdf
    Info: Found entity 1: lpm_divide_ucm
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_8kh.tdf
    Info: Found entity 1: sign_div_unsign_8kh
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_ive.tdf
    Info: Found entity 1: alt_u_div_ive
Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf
    Info: Found entity 1: add_sub_lkc
Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf
    Info: Found entity 1: add_sub_mkc
Info: Elaborated megafunction instantiation "lpm_divide:Mod2"
Info: Instantiated megafunction "lpm_divide:Mod2" with the following parameter:
    Info: Parameter "LPM_WIDTHN" = "6"
    Info: Parameter "LPM_WIDTHD" = "6"
    Info: Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
    Info: Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_45m.tdf
    Info: Found entity 1: lpm_divide_45m
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_bkh.tdf
    Info: Found entity 1: sign_div_unsign_bkh
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_ove.tdf
    Info: Found entity 1: alt_u_div_ove
Info: Elaborated megafunction instantiation "lpm_divide:Div1"
Info: Instantiated megafunction "lpm_divide:Div1" with the following parameter:
    Info: Parameter "LPM_WIDTHN" = "6"
    Info: Parameter "LPM_WIDTHD" = "4"
    Info: Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
    Info: Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_vcm.tdf
    Info: Found entity 1: lpm_divide_vcm
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_9kh.tdf
    Info: Found entity 1: sign_div_unsign_9kh
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_kve.tdf
    Info: Found entity 1: alt_u_div_kve
Info: Elaborated megafunction instantiation "lpm_divide:Mod0"
Info: Instantiated megafunction "lpm_divide:Mod0" with the following parameter:
    Info: Parameter "LPM_WIDTHN" = "5"
    Info: Parameter "LPM_WIDTHD" = "5"
    Info: Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
    Info: Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_25m.tdf
    Info: Found entity 1: lpm_divide_25m
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_akh.tdf
    Info: Found entity 1: sign_div_unsign_akh
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_lve.tdf
    Info: Found entity 1: alt_u_div_lve
Warning: Latch hourp[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal sw13
Warning: Latch hourp[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal sw13
Warning: Latch hourp[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal sw13
Warning: Latch hourp[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal sw13
Warning: Latch minp[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal sw13
Warning: Latch minp[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal sw13
Warning: Latch minp[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal sw13
Warning: Latch minp[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal sw13
Warning: Latch minp[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal sw13
Warning: Latch minp[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal sw13
Warning: Latch hourp[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal sw13
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning: Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state.
    Warning (13310): Register "hour[4]" is converted into an equivalent circuit using register "hour[4]~_emulated" and latch "hour[4]~latch"
    Warning (13310): Register "hour[3]" is converted into an equivalent circuit using register "hour[3]~_emulated" and latch "hour[3]~latch"
    Warning (13310): Register "hour[2]" is converted into an equivalent circuit using register "hour[2]~_emulated" and latch "hour[2]~latch"
    Warning (13310): Register "hour[1]" is converted into an equivalent circuit using register "hour[1]~_emulated" and latch "hour[1]~latch"
    Warning (13310): Register "min[0]" is converted into an equivalent circuit using register "min[0]~_emulated" and latch "min[0]~latch"
    Warning (13310): Register "min[1]" is converted into an equivalent circuit using register "min[1]~_emulated" and latch "min[1]~latch"
    Warning (13310): Register "min[5]" is converted into an equivalent circuit using register "min[5]~_emulated" and latch "min[5]~latch"
    Warning (13310): Register "min[4]" is converted into an equivalent circuit using register "min[4]~_emulated" and latch "min[4]~latch"
    Warning (13310): Register "min[3]" is converted into an equivalent circuit using register "min[3]~_emulated" and latch "min[3]~latch"
    Warning (13310): Register "min[2]" is converted into an equivalent circuit using register "min[2]~_emulated" and latch "min[2]~latch"
    Warning (13310): Register "hour[0]" is converted into an equivalent circuit using register "hour[0]~_emulated" and latch "hour[0]~latch"
Info: Implemented 432 device resources after synthesis - the final resource count might be different
    Info: Implemented 8 input pins
    Info: Implemented 16 output pins
    Info: Implemented 408 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 73 warnings
    Info: Peak virtual memory: 203 megabytes
    Info: Processing ended: Fri Dec 05 00:29:24 2008
    Info: Elapsed time: 00:00:04
    Info: Total CPU time (on all processors): 00:00:04