swatch.tan.qmsg

来自「swatch - quartus2 vhdl」· QMSG 代码 · 共 11 行 · 第 1/5 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register minp\[5\] register hour\[2\]~_emulated 47.22 MHz 21.176 ns Internal " "Info: Clock \"clk\" has Internal fmax of 47.22 MHz between source register \"minp\[5\]\" and destination register \"hour\[2\]~_emulated\" (period= 21.176 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.249 ns + Longest register register " "Info: + Longest register to register delay is 4.249 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns minp\[5\] 1 REG LCCOMB_X61_Y14_N2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X61_Y14_N2; Fanout = 5; REG Node = 'minp\[5\]'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { minp[5] } "NODE_NAME" } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.371 ns) + CELL(0.206 ns) 0.577 ns min\[5\]~head_lut 2 COMB LCCOMB_X61_Y14_N10 9 " "Info: 2: + IC(0.371 ns) + CELL(0.206 ns) = 0.577 ns; Loc. = LCCOMB_X61_Y14_N10; Fanout = 9; COMB Node = 'min\[5\]~head_lut'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.577 ns" { minp[5] min[5]~head_lut } "NODE_NAME" } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.083 ns) + CELL(0.206 ns) 1.866 ns LessThan2~77 3 COMB LCCOMB_X62_Y15_N2 7 " "Info: 3: + IC(1.083 ns) + CELL(0.206 ns) = 1.866 ns; Loc. = LCCOMB_X62_Y15_N2; Fanout = 7; COMB Node = 'LessThan2~77'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.289 ns" { min[5]~head_lut LessThan2~77 } "NODE_NAME" } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.704 ns) + CELL(0.202 ns) 2.772 ns hour\[4\]~174 4 COMB LCCOMB_X63_Y15_N18 5 " "Info: 4: + IC(0.704 ns) + CELL(0.202 ns) = 2.772 ns; Loc. = LCCOMB_X63_Y15_N18; Fanout = 5; COMB Node = 'hour\[4\]~174'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.906 ns" { LessThan2~77 hour[4]~174 } "NODE_NAME" } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.622 ns) + CELL(0.855 ns) 4.249 ns hour\[2\]~_emulated 5 REG LCFF_X64_Y15_N17 1 " "Info: 5: + IC(0.622 ns) + CELL(0.855 ns) = 4.249 ns; Loc. = LCFF_X64_Y15_N17; Fanout = 1; REG Node = 'hour\[2\]~_emulated'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.477 ns" { hour[4]~174 hour[2]~_emulated } "NODE_NAME" } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.469 ns ( 34.57 % ) " "Info: Total cell delay = 1.469 ns ( 34.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.780 ns ( 65.43 % ) " "Info: Total interconnect delay = 2.780 ns ( 65.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "4.249 ns" { minp[5] min[5]~head_lut LessThan2~77 hour[4]~174 hour[2]~_emulated } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "4.249 ns" { minp[5] {} min[5]~head_lut {} LessThan2~77 {} hour[4]~174 {} hour[2]~_emulated {} } { 0.000ns 0.371ns 1.083ns 0.704ns 0.622ns } { 0.000ns 0.206ns 0.206ns 0.202ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-6.379 ns - Smallest " "Info: - Smallest clock skew is -6.379 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.213 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.213 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns clk 1 CLK PIN_P2 3 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_P2; Fanout = 3; CLK Node = 'clk'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.349 ns clk~clkctrl 2 COMB CLKCTRL_G3 40 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.349 ns; Loc. = CLKCTRL_G3; Fanout = 40; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.239 ns" { clk clk~clkctrl } "NODE_NAME" } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.198 ns) + CELL(0.666 ns) 3.213 ns hour\[2\]~_emulated 3 REG LCFF_X64_Y15_N17 1 " "Info: 3: + IC(1.198 ns) + CELL(0.666 ns) = 3.213 ns; Loc. = LCFF_X64_Y15_N17; Fanout = 1; REG Node = 'hour\[2\]~_emulated'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.864 ns" { clk~clkctrl hour[2]~_emulated } "NODE_NAME" } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.776 ns ( 55.28 % ) " "Info: Total cell delay = 1.776 ns ( 55.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.437 ns ( 44.72 % ) " "Info: Total interconnect delay = 1.437 ns ( 44.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "3.213 ns" { clk clk~clkctrl hour[2]~_emulated } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "3.213 ns" { clk {} clk~combout {} clk~clkctrl {} hour[2]~_emulated {} } { 0.000ns 0.000ns 0.239ns 1.198ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.592 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 9.592 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns clk 1 CLK PIN_P2 3 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_P2; Fanout = 3; CLK Node = 'clk'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.320 ns) + CELL(0.970 ns) 3.400 ns sw13 2 REG LCFF_X5_Y18_N9 31 " "Info: 2: + IC(1.320 ns) + CELL(0.970 ns) = 3.400 ns; Loc. = LCFF_X5_Y18_N9; Fanout = 31; REG Node = 'sw13'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.290 ns" { clk sw13 } "NODE_NAME" } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.452 ns) + CELL(0.370 ns) 4.222 ns hourp\[0\]~467 3 COMB LCCOMB_X5_Y18_N4 2 " "Info: 3: + IC(0.452 ns) + CELL(0.370 ns) = 4.222 ns; Loc. = LCCOMB_X5_Y18_N4; Fanout = 2; COMB Node = 'hourp\[0\]~467'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.822 ns" { sw13 hourp[0]~467 } "NODE_NAME" } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.385 ns) + CELL(0.370 ns) 4.977 ns minp\[0\]~426 4 COMB LCCOMB_X5_Y18_N22 1 " "Info: 4: + IC(0.385 ns) + CELL(0.370 ns) = 4.977 ns; Loc. = LCCOMB_X5_Y18_N22; Fanout = 1; COMB Node = 'minp\[0\]~426'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.755 ns" { hourp[0]~467 minp[0]~426 } "NODE_NAME" } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.708 ns) + CELL(0.000 ns) 7.685 ns minp\[0\]~426clkctrl 5 COMB CLKCTRL_G14 6 " "Info: 5: + IC(2.708 ns) + CELL(0.000 ns) = 7.685 ns; Loc. = CLKCTRL_G14; Fanout = 6; COMB Node = 'minp\[0\]~426clkctrl'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.708 ns" { minp[0]~426 minp[0]~426clkctrl } "NODE_NAME" } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.701 ns) + CELL(0.206 ns) 9.592 ns minp\[5\] 6 REG LCCOMB_X61_Y14_N2 5 " "Info: 6: + IC(1.701 ns) + CELL(0.206 ns) = 9.592 ns; Loc. = LCCOMB_X61_Y14_N2; Fanout = 5; REG Node = 'minp\[5\]'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.907 ns" { minp[0]~426clkctrl minp[5] } "NODE_NAME" } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.026 ns ( 31.55 % ) " "Info: Total cell delay = 3.026 ns ( 31.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.566 ns ( 68.45 % ) " "Info: Total interconnect delay = 6.566 ns ( 68.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "9.592 ns" { clk sw13 hourp[0]~467 minp[0]~426 minp[0]~426clkctrl minp[5] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "9.592 ns" { clk {} clk~combout {} sw13 {} hourp[0]~467 {} minp[0]~426 {} minp[0]~426clkctrl {} minp[5] {} } { 0.000ns 0.000ns 1.320ns 0.452ns 0.385ns 2.708ns 1.701ns } { 0.000ns 1.110ns 0.970ns 0.370ns 0.370ns 0.000ns 0.206ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "3.213 ns" { clk clk~clkctrl hour[2]~_emulated } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "3.213 ns" { clk {} clk~combout {} clk~clkctrl {} hour[2]~_emulated {} } { 0.000ns 0.000ns 0.239ns 1.198ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "9.592 ns" { clk sw13 hourp[0]~467 minp[0]~426 minp[0]~426clkctrl minp[5] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "9.592 ns" { clk {} clk~combout {} sw13 {} hourp[0]~467 {} minp[0]~426 {} minp[0]~426clkctrl {} minp[5] {} } { 0.000ns 0.000ns 1.320ns 0.452ns 0.385ns 2.708ns 1.701ns } { 0.000ns 1.110ns 0.970ns 0.370ns 0.370ns 0.000ns 0.206ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 129 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 73 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 129 -1 0 } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 73 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "4.249 ns" { minp[5] min[5]~head_lut LessThan2~77 hour[4]~174 hour[2]~_emulated } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "4.249 ns" { minp[5] {} min[5]~head_lut {} LessThan2~77 {} hour[4]~174 {} hour[2]~_emulated {} } { 0.000ns 0.371ns 1.083ns 0.704ns 0.622ns } { 0.000ns 0.206ns 0.206ns 0.202ns 0.855ns } "" } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "3.213 ns" { clk clk~clkctrl hour[2]~_emulated } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "3.213 ns" { clk {} clk~combout {} clk~clkctrl {} hour[2]~_emulated {} } { 0.000ns 0.000ns 0.239ns 1.198ns } { 0.000ns 1.110ns 0.000ns 0.666ns } "" } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "9.592 ns" { clk sw13 hourp[0]~467 minp[0]~426 minp[0]~426clkctrl minp[5] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "9.592 ns" { clk {} clk~combout {} sw13 {} hourp[0]~467 {} minp[0]~426 {} minp[0]~426clkctrl {} minp[5] {} } { 0.000ns 0.000ns 1.320ns 0.452ns 0.385ns 2.708ns 1.701ns } { 0.000ns 1.110ns 0.970ns 0.370ns 0.370ns 0.000ns 0.206ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 11 " "Warning: Circuit may not operate. Detected 11 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "sw13 minp\[5\] clk 1.323 ns " "Info: Found hold time violation between source  pin or register \"sw13\" and destination pin or register \"minp\[5\]\" for clock \"clk\" (Hold time is 1.323 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "6.496 ns + Largest " "Info: + Largest clock skew is 6.496 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.592 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 9.592 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns clk 1 CLK PIN_P2 3 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_P2; Fanout = 3; CLK Node = 'clk'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.320 ns) + CELL(0.970 ns) 3.400 ns sw13 2 REG LCFF_X5_Y18_N9 31 " "Info: 2: + IC(1.320 ns) + CELL(0.970 ns) = 3.400 ns; Loc. = LCFF_X5_Y18_N9; Fanout = 31; REG Node = 'sw13'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.290 ns" { clk sw13 } "NODE_NAME" } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.452 ns) + CELL(0.370 ns) 4.222 ns hourp\[0\]~467 3 COMB LCCOMB_X5_Y18_N4 2 " "Info: 3: + IC(0.452 ns) + CELL(0.370 ns) = 4.222 ns; Loc. = LCCOMB_X5_Y18_N4; Fanout = 2; COMB Node = 'hourp\[0\]~467'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.822 ns" { sw13 hourp[0]~467 } "NODE_NAME" } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.385 ns) + CELL(0.370 ns) 4.977 ns minp\[0\]~426 4 COMB LCCOMB_X5_Y18_N22 1 " "Info: 4: + IC(0.385 ns) + CELL(0.370 ns) = 4.977 ns; Loc. = LCCOMB_X5_Y18_N22; Fanout = 1; COMB Node = 'minp\[0\]~426'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.755 ns" { hourp[0]~467 minp[0]~426 } "NODE_NAME" } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.708 ns) + CELL(0.000 ns) 7.685 ns minp\[0\]~426clkctrl 5 COMB CLKCTRL_G14 6 " "Info: 5: + IC(2.708 ns) + CELL(0.000 ns) = 7.685 ns; Loc. = CLKCTRL_G14; Fanout = 6; COMB Node = 'minp\[0\]~426clkctrl'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.708 ns" { minp[0]~426 minp[0]~426clkctrl } "NODE_NAME" } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.701 ns) + CELL(0.206 ns) 9.592 ns minp\[5\] 6 REG LCCOMB_X61_Y14_N2 5 " "Info: 6: + IC(1.701 ns) + CELL(0.206 ns) = 9.592 ns; Loc. = LCCOMB_X61_Y14_N2; Fanout = 5; REG Node = 'minp\[5\]'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.907 ns" { minp[0]~426clkctrl minp[5] } "NODE_NAME" } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.026 ns ( 31.55 % ) " "Info: Total cell delay = 3.026 ns ( 31.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.566 ns ( 68.45 % ) " "Info: Total interconnect delay = 6.566 ns ( 68.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "9.592 ns" { clk sw13 hourp[0]~467 minp[0]~426 minp[0]~426clkctrl minp[5] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "9.592 ns" { clk {} clk~combout {} sw13 {} hourp[0]~467 {} minp[0]~426 {} minp[0]~426clkctrl {} minp[5] {} } { 0.000ns 0.000ns 1.320ns 0.452ns 0.385ns 2.708ns 1.701ns } { 0.000ns 1.110ns 0.970ns 0.370ns 0.370ns 0.000ns 0.206ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.096 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.096 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns clk 1 CLK PIN_P2 3 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_P2; Fanout = 3; CLK Node = 'clk'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.320 ns) + CELL(0.666 ns) 3.096 ns sw13 2 REG LCFF_X5_Y18_N9 31 " "Info: 2: + IC(1.320 ns) + CELL(0.666 ns) = 3.096 ns; Loc. = LCFF_X5_Y18_N9; Fanout = 31; REG Node = 'sw13'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.986 ns" { clk sw13 } "NODE_NAME" } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.776 ns ( 57.36 % ) " "Info: Total cell delay = 1.776 ns ( 57.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.320 ns ( 42.64 % ) " "Info: Total interconnect delay = 1.320 ns ( 42.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "3.096 ns" { clk sw13 } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "3.096 ns" { clk {} clk~combout {} sw13 {} } { 0.000ns 0.000ns 1.320ns } { 0.000ns 1.110ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "9.592 ns" { clk sw13 hourp[0]~467 minp[0]~426 minp[0]~426clkctrl minp[5] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "9.592 ns" { clk {} clk~combout {} sw13 {} hourp[0]~467 {} minp[0]~426 {} minp[0]~426clkctrl {} minp[5] {} } { 0.000ns 0.000ns 1.320ns 0.452ns 0.385ns 2.708ns 1.701ns } { 0.000ns 1.110ns 0.970ns 0.370ns 0.370ns 0.000ns 0.206ns } "" } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "3.096 ns" { clk sw13 } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "3.096 ns" { clk {} clk~combout {} sw13 {} } { 0.000ns 0.000ns 1.320ns } { 0.000ns 1.110ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 28 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.869 ns - Shortest register register " "Info: - Shortest register to register delay is 4.869 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sw13 1 REG LCFF_X5_Y18_N9 31 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X5_Y18_N9; Fanout = 31; REG Node = 'sw13'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { sw13 } "NODE_NAME" } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.763 ns) + CELL(0.370 ns) 4.133 ns Add5~722 2 COMB LCCOMB_X61_Y14_N14 1 " "Info: 2: + IC(3.763 ns) + CELL(0.370 ns) = 4.133 ns; Loc. = LCCOMB_X61_Y14_N14; Fanout = 1; COMB Node = 'Add5~722'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "4.133 ns" { sw13 Add5~722 } "NODE_NAME" } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 138 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.370 ns) + CELL(0.366 ns) 4.869 ns minp\[5\] 3 REG LCCOMB_X61_Y14_N2 5 " "Info: 3: + IC(0.370 ns) + CELL(0.366 ns) = 4.869 ns; Loc. = LCCOMB_X61_Y14_N2; Fanout = 5; REG Node = 'minp\[5\]'" {  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.736 ns" { Add5~722 minp[5] } "NODE_NAME" } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.736 ns ( 15.12 % ) " "Info: Total cell delay = 0.736 ns ( 15.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.133 ns ( 84.88 % ) " "Info: Total interconnect delay = 4.133 ns ( 84.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "4.869 ns" { sw13 Add5~722 minp[5] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "4.869 ns" { sw13 {} Add5~722 {} minp[5] {} } { 0.000ns 3.763ns 0.370ns } { 0.000ns 0.370ns 0.366ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 129 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 28 -1 0 } } { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 129 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 0}  } { { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "9.592 ns" { clk sw13 hourp[0]~467 minp[0]~426 minp[0]~426clkctrl minp[5] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "9.592 ns" { clk {} clk~combout {} sw13 {} hourp[0]~467 {} minp[0]~426 {} minp[0]~426clkctrl {} minp[5] {} } { 0.000ns 0.000ns 1.320ns 0.452ns 0.385ns 2.708ns 1.701ns } { 0.000ns 1.110ns 0.970ns 0.370ns 0.370ns 0.000ns 0.206ns } "" } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "3.096 ns" { clk sw13 } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "3.096 ns" { clk {} clk~combout {} sw13 {} } { 0.000ns 0.000ns 1.320ns } { 0.000ns 1.110ns 0.666ns } "" } } { "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80sp1/quartus/bin/TimingClosureFloorplan.fld" "" "4.869 ns" { sw13 Add5~722 minp[5] } "NODE_NAME" } } { "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80sp1/quartus/bin/Technology_Viewer.qrui" "4.869 ns" { sw13 {} Add5~722 {} minp[5] {} } { 0.000ns 3.763ns 0.370ns } { 0.000ns 0.370ns 0.366ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0 0}