swatch.map.qmsg

来自「swatch - quartus2 vhdl」· QMSG 代码 · 共 104 行 · 第 1/4 页

{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_divide:Div1 " "Info: Instantiated megafunction \"lpm_divide:Div1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 6 " "Info: Parameter \"LPM_WIDTHN\" = \"6\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Info: Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Info: Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Info: Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 201 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_vcm.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_vcm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_vcm " "Info: Found entity 1: lpm_divide_vcm" {  } { { "db/lpm_divide_vcm.tdf" "" { Text "C:/Users/CSI/Desktop/swatch/db/lpm_divide_vcm.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_9kh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_9kh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_9kh " "Info: Found entity 1: sign_div_unsign_9kh" {  } { { "db/sign_div_unsign_9kh.tdf" "" { Text "C:/Users/CSI/Desktop/swatch/db/sign_div_unsign_9kh.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_kve.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_kve.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_kve " "Info: Found entity 1: alt_u_div_kve" {  } { { "db/alt_u_div_kve.tdf" "" { Text "C:/Users/CSI/Desktop/swatch/db/alt_u_div_kve.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_divide:Mod0 " "Info: Elaborated megafunction instantiation \"lpm_divide:Mod0\"" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 200 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_divide:Mod0 " "Info: Instantiated megafunction \"lpm_divide:Mod0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 5 " "Info: Parameter \"LPM_WIDTHN\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 5 " "Info: Parameter \"LPM_WIDTHD\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Info: Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Info: Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 200 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_25m.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_25m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_25m " "Info: Found entity 1: lpm_divide_25m" {  } { { "db/lpm_divide_25m.tdf" "" { Text "C:/Users/CSI/Desktop/swatch/db/lpm_divide_25m.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_akh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_akh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_akh " "Info: Found entity 1: sign_div_unsign_akh" {  } { { "db/sign_div_unsign_akh.tdf" "" { Text "C:/Users/CSI/Desktop/swatch/db/sign_div_unsign_akh.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_lve.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_lve.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_lve " "Info: Found entity 1: alt_u_div_lve" {  } { { "db/alt_u_div_lve.tdf" "" { Text "C:/Users/CSI/Desktop/swatch/db/alt_u_div_lve.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "hourp\[4\] " "Warning: Latch hourp\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA sw13 " "Warning: Ports D and ENA on the latch are fed by the same signal sw13" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 28 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 129 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "hourp\[3\] " "Warning: Latch hourp\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA sw13 " "Warning: Ports D and ENA on the latch are fed by the same signal sw13" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 28 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 129 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "hourp\[2\] " "Warning: Latch hourp\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA sw13 " "Warning: Ports D and ENA on the latch are fed by the same signal sw13" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 28 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 129 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "hourp\[1\] " "Warning: Latch hourp\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA sw13 " "Warning: Ports D and ENA on the latch are fed by the same signal sw13" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 28 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 129 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "minp\[0\] " "Warning: Latch minp\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA sw13 " "Warning: Ports D and ENA on the latch are fed by the same signal sw13" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 28 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 129 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "minp\[1\] " "Warning: Latch minp\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA sw13 " "Warning: Ports D and ENA on the latch are fed by the same signal sw13" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 28 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 129 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "minp\[5\] " "Warning: Latch minp\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA sw13 " "Warning: Ports D and ENA on the latch are fed by the same signal sw13" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 28 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 129 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "minp\[4\] " "Warning: Latch minp\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA sw13 " "Warning: Ports D and ENA on the latch are fed by the same signal sw13" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 28 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 129 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "minp\[3\] " "Warning: Latch minp\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA sw13 " "Warning: Ports D and ENA on the latch are fed by the same signal sw13" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 28 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 129 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "minp\[2\] " "Warning: Latch minp\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA sw13 " "Warning: Ports D and ENA on the latch are fed by the same signal sw13" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 28 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 129 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "hourp\[0\] " "Warning: Latch hourp\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA sw13 " "Warning: Ports D and ENA on the latch are fed by the same signal sw13" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 28 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 129 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 180 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_CREATED_ALOAD_CCT" "" "Warning: Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state." { { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "hour\[4\] hour\[4\]~_emulated hour\[4\]~latch " "Warning (13310): Register \"hour\[4\]\" is converted into an equivalent circuit using register \"hour\[4\]~_emulated\" and latch \"hour\[4\]~latch\"" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 73 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "hour\[3\] hour\[3\]~_emulated hour\[3\]~latch " "Warning (13310): Register \"hour\[3\]\" is converted into an equivalent circuit using register \"hour\[3\]~_emulated\" and latch \"hour\[3\]~latch\"" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 73 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "hour\[2\] hour\[2\]~_emulated hour\[2\]~latch " "Warning (13310): Register \"hour\[2\]\" is converted into an equivalent circuit using register \"hour\[2\]~_emulated\" and latch \"hour\[2\]~latch\"" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 73 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "hour\[1\] hour\[1\]~_emulated hour\[1\]~latch " "Warning (13310): Register \"hour\[1\]\" is converted into an equivalent circuit using register \"hour\[1\]~_emulated\" and latch \"hour\[1\]~latch\"" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 73 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "min\[0\] min\[0\]~_emulated min\[0\]~latch " "Warning (13310): Register \"min\[0\]\" is converted into an equivalent circuit using register \"min\[0\]~_emulated\" and latch \"min\[0\]~latch\"" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 73 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "min\[1\] min\[1\]~_emulated min\[1\]~latch " "Warning (13310): Register \"min\[1\]\" is converted into an equivalent circuit using register \"min\[1\]~_emulated\" and latch \"min\[1\]~latch\"" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 73 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "min\[5\] min\[5\]~_emulated min\[5\]~latch " "Warning (13310): Register \"min\[5\]\" is converted into an equivalent circuit using register \"min\[5\]~_emulated\" and latch \"min\[5\]~latch\"" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 73 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "min\[4\] min\[4\]~_emulated min\[4\]~latch " "Warning (13310): Register \"min\[4\]\" is converted into an equivalent circuit using register \"min\[4\]~_emulated\" and latch \"min\[4\]~latch\"" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 73 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "min\[3\] min\[3\]~_emulated min\[3\]~latch " "Warning (13310): Register \"min\[3\]\" is converted into an equivalent circuit using register \"min\[3\]~_emulated\" and latch \"min\[3\]~latch\"" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 73 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "min\[2\] min\[2\]~_emulated min\[2\]~latch " "Warning (13310): Register \"min\[2\]\" is converted into an equivalent circuit using register \"min\[2\]~_emulated\" and latch \"min\[2\]~latch\"" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 73 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "hour\[0\] hour\[0\]~_emulated hour\[0\]~latch " "Warning (13310): Register \"hour\[0\]\" is converted into an equivalent circuit using register \"hour\[0\]~_emulated\" and latch \"hour\[0\]~latch\"" {  } { { "swatch.vhd" "" { Text "C:/Users/CSI/Desktop/swatch/swatch.vhd" 73 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state." 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "432 " "Info: Implemented 432 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Info: Implemented 8 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "408 " "Info: Implemented 408 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 73 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 73 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "203 " "Info: Peak virtual memory: 203 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 05 00:29:24 2008 " "Info: Processing ended: Fri Dec 05 00:29:24 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Info: Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}