dcm_adv.v

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  else
     clkfx_out = clkfx_out_ph;


always @(locked_out or posedge rst_in or clkfx_out_avg )
      if (rst_in == 1) 
         clkfx_out_avg  <= 0;
      else if (locked_out == 1) 
         if (DFS_OSCILLATOR_MODE == "AVE_FREQ_LOCK")
            clkfx_out_avg  <= #(period_fxavg) ~clkfx_out_avg;

always @(posedge clkin_ps or posedge clkin_lost_out or posedge rst_in) 
  if (rst_in == 1)
         clkfx_out_ph  = 0;
  else if (clkin_lost_out == 1'b1 ) begin
           if (locked_out == 1)
            @(negedge rst_reg[2]);
        end
  else
   if (lock_out[1] == 1 && DFS_OSCILLATOR_MODE == "PHASE_FREQ_LOCK") begin
    if (lock_out[1] == 1 ) begin
	clkfx_out_ph = 1'b1;
	for (p = 0; p < (numerator * 2 - 1); p = p + 1) begin
	    #(period_fx);
	    if (p < remain_fx)
		#1;
	    clkfx_out_ph = !clkfx_out_ph;
	end
	if (period_fx > (period / 2)) begin
	    #(period_fx - (period / 2));
	end
    end
  end

//
// detect_first_time_locked
//

always @(posedge locked_out)
   if (first_time_locked == 0) 
      first_time_locked <= 1;

always @(ps_overflow_out or clkin_lost_out or clkfx_lost_out or
         clkfb_lost_out or en_status)
  if ( en_status != 1) 
     do_out_s[3:0] = 4'b0;
  else
  begin
     do_out_s[0] = ps_overflow_out;
     do_out_s[1] = clkin_lost_out;
     do_out_s[2] = clkfx_lost_out;
     do_out_s[3] = clkfb_lost_out;
  end

 assign do_out = (do_stat_en == 0) ? do_out_drp1 : do_out_s;

always @(posedge rst_in or posedge LOCKED)
  if (rst_in == 1)
      en_status <= 0;
   else
      en_status <= 1;

//
// drp process
//

always @(posedge dclk_in or posedge gsr_in)
begin
  if (gsr_in == 1) begin
       drp_lock <= 0;
       ps_in_drp <= 0;
       ps_kick_off_cmd <= 0;
       do_out_drp <= 16'b0;
       do_out_drp1 <= 16'b0;
       do_stat_en <= 1;
       drdy_out <= 0;
    end 
  else begin
    valid_daddr = addr_is_valid(daddr_in);
    if (DEN == 1) begin 
        if (drp_lock == 1)
          $display(" Warning : DEN is high at DCM_ADV instance %m at time %t. Please wait for DRDY signal before next read/write operation through DRP. ", $time);
        else  begin
          drp_lock <= 1;
       
          if (DWE == 0 && sim_device_type == 1 ) begin
           if (daddr_in == `DCM_DEFAULT_STATUS_ADDR)
               do_stat_en <= 1;
           else begin
               do_stat_en <= 0;
               if (daddr_in == `DFS_FREQ_MODE_ADDR)
                   do_out_drp <= dfs_mode_reg;
               else if (daddr_in == `DLL_FREQ_MODE_ADDR)
                   do_out_drp <= dll_mode_reg;
               else if (daddr_in == `CLKFX_MULTIPLY_ADDR)
                   do_out_drp <= clkfx_md_reg;
               else if (daddr_in == `CLKIN_DIV_BY2_ADDR)
                   do_out_drp <= clkin_div2_reg;
               else 
                   do_out_drp <= 16'b0;
           end
          end
              
          if (DWE == 1) begin
            if (valid_daddr) begin 
              if (daddr_in == `CLKFX_MULTIPLY_ADDR) begin 
                  if (sim_device_type == 1) begin
                     clkfx_divide_drp <= di_in[7:0] + 1;
                     clkfx_multiply_drp <= di_in[15:8] + 1;
                     clkfx_md_reg <= di_in;
                  end
                  else
                     clkfx_multiply_drp <= di_in[4:0] + 1;
              end
              else if (daddr_in == `CLKFX_DIVIDE_ADDR && sim_device_type == 0) begin 
                clkfx_divide_drp <= di_in[4:0] + 1;
              end
              else if (daddr_in == `PHASE_SHIFT_ADDR) begin 
                ps_drp <= di_in[10:0];
              end
              else if (daddr_in == `PHASE_SHIFT_KICK_OFF_ADDR) begin 
                if (ps_kick_off_cmd == 0) begin
                  ps_kick_off_cmd <= 1;
                  ps_in_drp <= ps_drp;
                    if (ps_in < ps_drp) 
                      inc_dec <= 1;
                    else if (ps_in > ps_drp) 
                      inc_dec <= 0;
                 end
             end
             else if (daddr_in == `DFS_FREQ_MODE_ADDR && sim_device_type == 1) begin
                   dfs_mode_reg <= di_in;
             end
             else if (daddr_in == `DLL_FREQ_MODE_ADDR && sim_device_type == 1) begin
                   dll_mode_reg <= di_in;
             end
             else if (daddr_in == `CLKIN_DIV_BY2_ADDR && sim_device_type == 1) begin
                   clkin_div2_reg <= di_in;
             end
             else 
                $display(" Warning : Address DADDR=%b is unsupported at DCM_ADV instance %m at time %t.  ",  daddr_in, $time);

           end
         end
      end
    end
    if (ps_drp_lock == 1)  
            if (ps_kick_off_cmd == 1)
               ps_kick_off_cmd <= 0;

    if ( drp_lock == 1)
         drp_lock1 <= 1;

    if ( drp_lock1 == 1) begin
          drp_lock <= 0;
          drp_lock1 <= 0;
          drdy_out <= 1;
          do_out_drp1 <= do_out_drp;
          do_out_drp <= 16'b0;
    end

    if (drdy_out == 1) begin
        drdy_out <= 0;
        do_out_drp1 <= 16'b0;
    end

  end
end

function addr_is_valid;
input [6:0] daddr_funcin;
begin
  addr_is_valid = 1;
  for (i=0; i<=6; i=i+1)
    if ( daddr_funcin[i] != 0 && daddr_funcin[i] != 1)
       addr_is_valid = 0;
end
endfunction

// end process drp;

//
//   drive_drdy_out  process
//

//always @(drp_lock or dclk_in or gsr_in)
//    @(negedge drp_lock)
//      @(posedge dclk_in) begin
//         if (gsr_in == 0) 
//            drdy_out = 1;
//         @(posedge dclk_in)
//         drdy_out = 0;
//    end

//
// generate all output signal
//

always @(rst_in)
if (rst_in) begin
   assign CLK0 = 0;
   assign CLK90 = 0;
   assign CLK180 = 0;
   assign CLK270 = 0;
   assign CLK2X = 0;
   assign CLK2X180 =0;
   assign CLKDV = 0;
   assign CLKFX = 0;
   assign CLKFX180 = 0;
end
else begin
   deassign CLK0;
   deassign CLK90;
   deassign CLK180;
   deassign CLK270;
   deassign CLK2X;
   deassign CLK2X180;
   deassign CLKDV;
   deassign CLKFX;
   deassign CLKFX180;
end

always @(clk0_out) begin
    CLK0 <= #(clkout_delay) clk0_out;
    CLK90 <= #(clkout_delay + period / 4) clk0_out;
      CLK180 <= #(clkout_delay + period / 2) clk0_out;
      CLK270 <= #(clkout_delay + period / 4) ~clk0_out;
  end

always @(clk2x_out)  begin
    CLK2X <= #(clkout_delay) clk2x_out;
    CLK2X180 <= #(clkout_delay) ~clk2x_out ;
end


always @(clkdv_out) 
    CLKDV <= #(clkout_delay) clkdv_out;

always @(clkfx_out )
    CLKFX <= #(clkout_delay) clkfx_out;

always @( clkfx_out or  first_time_locked or locked_out) begin
  if ( ~first_time_locked)
     CLKFX180 <= 0;
  else
    CLKFX180 <=  #(clkout_delay) ~clkfx_out;
end


endmodule

//////////////////////////////////////////////////////

module dcm_adv_clock_divide_by_2 (clock, clock_type, clock_out, rst);
input clock;
input clock_type;
input rst;
output clock_out;

reg clock_out;
reg clock_div2;
reg [2:0] rst_reg;
wire clk_src;

initial begin
    clock_out = 1'b0;
    clock_div2 = 1'b0;
end

always @(posedge clock)
    clock_div2 <= ~clock_div2;

always @(posedge clock) begin
    rst_reg[0] <= rst;
    rst_reg[1] <= rst_reg[0] & rst;
    rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst;
end

assign clk_src = (clock_type) ? clock_div2 : clock;

always @(clk_src or rst or rst_reg)
    if (rst == 1'b0)
        clock_out = clk_src;
    else if (rst == 1'b1) begin
        clock_out = 1'b0;
        @(negedge rst_reg[2]);
        if (clk_src == 1'b1)
          @(negedge clk_src);
    end


endmodule

module dcm_adv_maximum_period_check (clock,  rst);
parameter clock_name = "";
parameter maximum_period = 0;
input clock;
input rst;

time clock_edge;
time clock_period;

initial begin
    clock_edge = 0;
    clock_period = 0;
end

always @(posedge clock )
begin
    clock_edge <= $time;
    clock_period <= $time - clock_edge;
    if (clock_period > maximum_period && rst == 0 ) begin
	$display(" Warning : Input clock period of, %1.3f ns, on the %s port of instance %m exceeds allowed value of %1.3f ns at simulation time %1.3f ns.", clock_period/1000.0, clock_name, maximum_period/1000.0, $time/1000.0);
    end
end
endmodule

module dcm_adv_clock_lost (clock, enable, lost, rst);
input clock;
input enable;
input rst;
output lost;

reg lost_r, lost_f, lost;

time clock_edge;
reg [63:0] period;
reg clock_low, clock_high;
reg clock_posedge, clock_negedge;
reg clock_second_pos, clock_second_neg;

initial begin
    clock_edge = 0;
    clock_high = 0;
    clock_low = 0;
    lost_r = 0;
    lost_f = 0;
    period = 0;
    clock_posedge = 0;
    clock_negedge = 0;
    clock_second_pos = 0;
    clock_second_neg = 0;
end

always @(posedge clock or negedge clock or posedge rst)
  if (rst) begin
     clock_second_pos <= 0;
     clock_second_neg <= 0;
  end
  else if (clock)
     clock_second_pos <= 1;
  else if (~clock)
     clock_second_neg <= 1;

always @(posedge clock or posedge rst)
  if (rst) begin
    period <= 0;
  end
  else begin
    clock_edge <= $time;
    if (period != 0 && (($time - clock_edge) <= (1.5 * period)))
        period <= $time - clock_edge;
    else if (period != 0 && (($time - clock_edge) > (1.5 * period)))
        period <= 0;
    else if ((period == 0) && (clock_edge != 0) && clock_second_pos == 1)
        period <= $time - clock_edge;
  end

always @(posedge clock or posedge rst)
  if (rst) 
    lost_r <= 0;
  else 
  if (enable == 1 && clock_second_pos == 1) begin
      #1;
      if ( period != 0)
         lost_r <= 0;
      #((period * 9.1) / 10)
      if ((clock_low != 1'b1) && (clock_posedge != 1'b1) && rst == 0)
        lost_r <= 1;
    end

always @(negedge clock or posedge rst)
  if (rst==1) begin
     lost_f <= 0;
   end
   else begin
     if (enable == 1 && clock_second_neg == 1) begin
      if ( period != 0)
        lost_f <= 0;
      #((period * 9.1) / 10)
      if ((clock_high != 1'b1) && (clock_negedge != 1'b1) && rst == 0)
        lost_f <= 1;
      end
  end

always @( lost_r or  lost_f or enable)
  if (enable == 1) 
         lost = lost_r | lost_f;
  else
        lost = 0;

always @(posedge clock or negedge clock or posedge rst)
  if (rst==1) begin
           clock_low   <= 1'b0;
           clock_high  <= 1'b0;
           clock_posedge  <= 1'b0;
           clock_negedge <= 1'b0;
  end
  else 
    if (clock ==1) begin
           clock_low   <= 1'b0;
           clock_high  <= 1'b1;
           clock_posedge  <= 1'b0;
           clock_negedge <= 1'b1;
    end
    else if (clock == 0) begin
           clock_low   <= 1'b1;
           clock_high  <= 1'b0;
           clock_posedge  <= 1'b1;
           clock_negedge <= 1'b0;
    end

endmodule