dcm_adv.v

DDR2源代码 DDR2源代码 DDR2源代码

		ps_lock <= 1;
	    end
     end
     if (ps_type == 3'b101)  begin
          if (psen_in == 1) begin
            if (ps_lock == 1) begin
              $display(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift. ");
            end
            else
            begin
              if (psincdec_in == 1) begin
                if (ps_in_curr == ps_max) 
                  ps_overflow_out <= 1;
                else if (ps_in_curr * tap_delay_step > FINE_SHIFT_RANGE) 
                  ps_overflow_out <= 1;
                else
                 begin
                  ps_in_ps <= ps_in_curr + 1;
                  ps_overflow_out <= 0;
                end
                ps_lock <= 1;
              end
              else if (psincdec_in == 0) begin
                if (ps_in_curr == ps_min) 
                  ps_overflow_out <= 1;
                else if (ps_in_curr * tap_delay_step > FINE_SHIFT_RANGE) 
                  ps_overflow_out <= 1;
                else
                begin
                  ps_in_ps <= ps_in_curr - 1;
                  ps_overflow_out <= 0;
                end
                ps_lock <= 1;
              end
            end
          end
     end
     if ( psdone_out == 1)
            ps_lock <= 0;
end

always @(posedge clkin_ps or posedge rst_in)
  if (rst_in) begin
     single_step_lock <= 0;
     ps_in_psdrp <= ps_in;
     ps_delay_drp <= 0;
  end
  else begin
     if (ps_type == 3'b101) begin
        if (ps_drp_lock == 1) begin 
            if (inc_dec == 1) begin 
              if (ps_in_curr < ps_in_drp) begin 
                if (single_step_lock == 0) 
                begin
                  single_step_lock <= 1;
                  ps_in_psdrp <= ps_in_curr + 1;
                  ps_delay_drp <= ps_delay + tap_delay_step;
                end
               end
              else if (ps_in_curr == ps_in_drp) 
                ps_drp_lock <= 0;
            end
            else if (inc_dec == 0) begin 
              if (ps_in_curr > ps_in_drp) begin
                if (single_step_lock == 0) 
                begin 
                  single_step_lock <= 1;
                  ps_in_psdrp <= ps_in_curr - 1;
                  ps_delay_drp <= ps_delay - tap_delay_step;
                end
              end
              else if (ps_in_psdrp == ps_in_drp) 
                ps_drp_lock <= 0;
            end
        end

    if ( single_step_lock_tmp == 1)
         single_step_lock <= 0;
  
    if (ps_drp_lock_tmp == 1)
         ps_drp_lock <= 1;
  end
end

always @( single_step_lock or clkin_ps)
begin
      @( posedge single_step_lock)
      @( posedge clkin_ps)
      @( posedge clkin_ps)
      @( posedge clkin_ps)
         single_step_lock_tmp <= 1;
      @( posedge clkin_ps)
         single_step_lock_tmp <= 0;
end

always @( ps_kick_off_cmd or dclk_in or clkin_in or ps_drp_lock )
begin
      @(posedge ps_kick_off_cmd)
      @( posedge dclk_in)
      @( posedge dclk_in)
      @( posedge clkin_in)
      @( posedge clkin_in)
      @( posedge clkin_in)
      @( posedge clkin_in)
      @( posedge clkin_in)
         ps_drp_lock_tmp <= 1;
      @( posedge ps_drp_lock)
         ps_drp_lock_tmp <= 0;
end

always @(posedge ps_lock or negedge ps_drp_lock )
   if (ps_type != 3'b000 || ps_type != 3'b001) begin
        @(posedge clkin_ps)
        @(posedge clkin_ps)
        @(posedge clkin_ps)
        @(posedge clkin_ps)
        @(posedge psclk_in)
        @(posedge psclk_in)
          begin
            psdone_out = 1;
            @(posedge psclk_in);
               psdone_out = 0;
          end
   end

//
// determine clock period
//

always @(period_orig)
    period_stop_ck = period_orig * clock_stopped_factor;


always @(posedge clkin_div or negedge clkin_div or posedge rst_in) 
   if ( rst_in == 1)
   begin
     clkin_period[0] <= 0;
     clkin_period[1] <= 0;
     clkin_period[2] <= 0;
     clkin_edge <= 0;
   end
   else 
    if (clkin_div == 1) begin
       clkin_edge <= $time;
       clkin_period[2] <= clkin_period[1];
       clkin_period[1] <= clkin_period[0];
       if (clkin_edge != 0)
	   clkin_period[0] <= $time - clkin_edge;
      end
    else if (clkin_div == 0) 
      if (lock_period == 1) begin
        if (100000000 < clkin_period[0]/1000) 
        begin
        end
//        else if ((period_orig * 2 < clkin_period[0]) && (clock_stopped == 0)) begin
        else if ((period_stop_ck <= clkin_period[0]) && (clock_stopped == 0)) begin
          clkin_period[0] <= clkin_period[1];
        end
      end

//
// evaluate_clock_period process
//
always @(negedge clkin_div or posedge rst_in)
  if (rst_in == 1) begin
      lock_period <= 0;
      clock_stopped <= 1;
      period_fxtmp <= 0;
  end
  else begin
    if (lock_period == 1'b0) begin
	if ((clkin_period[0] != 0) &&
		(clkin_period[0] - cycle_jitter <= clkin_period[1]) &&
		(clkin_period[1] <= clkin_period[0] + cycle_jitter) &&
		(clkin_period[1] - cycle_jitter <= clkin_period[2]) &&
		(clkin_period[2] <= clkin_period[1] + cycle_jitter)) begin
	    lock_period <= 1;
	    period_orig <= (clkin_period[0] +
			    clkin_period[1] +
			    clkin_period[2]) / 3;
	    period_fxtmp <= (clkin_period[0] +
			    clkin_period[1] +
			    clkin_period[2]) / 3;
	    period <= clkin_period[0];
	end
    end
    else if (lock_period == 1'b1) begin
	if (100000000 < (clkin_period[0] / 1000)) begin
	    $display(" Warning : CLKIN stopped toggling on instance %m exceeds %d ms.  Current CLKIN Period = %1.3f ns.", 10000, clkin_period[0] / 1000.0);
	    lock_period <= 0;
	    @(negedge rst_reg[2]);
	end
//	else if ((period_orig * 2 < clkin_period[0]) && clock_stopped == 1'b0) begin
	else if ((period_stop_ck <= clkin_period[0]) && clock_stopped == 1'b0) begin
//	    clkin_period[0] = clkin_period[1];
	    clock_stopped <= 1'b1;
	end
	else if ((clkin_period[0] < period_orig - period_jitter) ||
		(period_orig + period_jitter < clkin_period[0])) begin
	    $display(" Warning : Input Clock Period Jitter on instance %m exceeds %1.3f ns.  Locked CLKIN Period = %1.3f.  Current CLKIN Period = %1.3f.", period_jitter / 1000.0, period_orig / 1000.0, clkin_period[0] / 1000.0);
	    lock_period <= 0;
	    @(negedge rst_reg[2]);
	end
	else if ((clkin_period[0] < clkin_period[1] - cycle_jitter) ||
		(clkin_period[1] + cycle_jitter < clkin_period[0])) begin
	    $display(" Warning : Input Clock Cycle-Cycle Jitter on instance %m exceeds %1.3f ns.  Previous CLKIN Period = %1.3f.  Current CLKIN Period = %1.3f.", cycle_jitter / 1000.0, clkin_period[1] / 1000.0, clkin_period[0] / 1000.0);
	    lock_period <= 0;
	    @(negedge rst_reg[2]);
	end
	else begin
	    period <= clkin_period[0];
	    clock_stopped <= 1'b0;
	    period_fxtmp <= (clkin_period[0] +
			    clkin_period[1] +
			    clkin_period[2]) / 3;
	end
    end
end

  assign #(period/2) lock_period_dly = lock_period;
  assign lock_period_pulse = (lock_period==1 && lock_period_dly==0) ? 1 : 0;
//
// determine clock delay
//


//always @(posedge lock_period or posedge rst_in) begin
always @(posedge lock_ps_dly or posedge rst_in) 
  if (rst_in) begin
    fb_delay  <= 0;
    fb_delay_found <= 0;
  end
  else begin
    if (lock_period && clkfb_type != 0) begin
	if (clkfb_type == 1) begin
	    @(posedge CLK0 or rst_in)
		delay_edge = $time;
	end
	else if (clkfb_type == 2) begin
	    @(posedge CLK2X or rst_in)
		delay_edge = $time;
	end
	@(posedge clkfb_in or rst_in) begin
	  fb_delay <= ($time - delay_edge) % period_orig;
          fb_delay_found <= 1;
        end
    end
  end

//
// determine feedback lock
//

always @(posedge clkfb_in or posedge rst_in) begin
  if (rst_in)
      clkfb_window <= 0;
  else begin
    #0  clkfb_window <= 1;
    #cycle_jitter clkfb_window <= 0;
  end
end

always @(posedge clkin_fb or posedge rst_in) begin
  if (rst_in)
      clkin_window <= 0;
  else begin
    #0  clkin_window <= 1;
    #cycle_jitter clkin_window <= 0;
  end
end

always @(posedge clkin_fb or posedge rst_in) begin
  if (rst_in)
     lock_clkin <= 0;
  else begin
    #1
    if ((clkfb_window && fb_delay_found ) || (clkin_lost_out == 1'b1 && lock_out[0]==1'b1))
	lock_clkin <= 1;
    else
      if (chk_enable ==1)
	lock_clkin <= 0;
  end
end

always @(posedge clkfb_in or posedge rst_in) begin
  if (rst_in)
    lock_clkfb <= 0;
  else begin
    #1
    if ((clkin_window && fb_delay_found) || (clkin_lost_out == 1'b1 && lock_out[0]==1'b1)) 
	lock_clkfb <= 1;
    else
      if (chk_enable ==1)
	lock_clkfb <= 0;
  end
end

always @(negedge clkin_fb or posedge rst_in) begin
  if (rst_in)
    lock_delay <= 0;
  else
    lock_delay <= lock_clkin || lock_clkfb;
end

//
// generate lock signal
//

   assign locked_out_out = (rst_flag) ? 1'bx : locked_out;

always @(posedge clkin_ps or posedge rst_in) 
  if (rst_in) begin
      lock_out <= 2'b00;
      locked_out <=0;
  end
  else begin
    if (clkfb_type == 0)
        lock_out[0] <= lock_period;
    else
        lock_out[0] <= lock_period & lock_delay & lock_fb;
    lock_out[1] <= lock_out[0];
    locked_out <= lock_out[1];
  end

always @(negedge clkin_ps or posedge rst_in)
  if (rst_in)
    lock_out1_neg <= 0;
  else
    lock_out1_neg <= lock_out[1];


//
// generate the clk1x_out
//

always @(posedge clkin_ps or negedge clkin_ps or posedge rst_in)
  if (rst_in)
      clk0_out <= 0;
  else if (clkin_ps ==1)
       if (clk1x_type==1 && lock_out[0]) begin
          clk0_out <= 1;
          #(period / 2);
          clk0_out <= 0;
       end
       else 
          clk0_out <= 1;
    else if (clkin_ps == 0 && ((clk1x_type && lock_out[0]) == 0 || (lock_out[0] ==1 && lock_out[1] == 0)))
          clk0_out <= 0;

//
// generate the clk2x_out
//

always @(posedge clkin_ps or posedge rst_in )
  if (rst_in)
     clk2x_out <= 0;
  else begin
    clk2x_out <= 1;
    #(period / 4)
    clk2x_out <= 0;
    if (lock_out[0]) begin
	#(period / 4)
	clk2x_out <= 1;
	#(period / 4)
	clk2x_out <= 0;
    end
    else begin
	#(period / 2);
    end
end

//
// generate the clkdv_out
//

always @(posedge clkin_ps or negedge clkin_ps or posedge rst_in) 
  if (rst_in) begin
       clkdv_out <= 1'b0;
       clkdv_cnt <= 0;
  end
  else
    if (lock_out1_neg) begin
      if (clkdv_cnt >= divide_type -1)
           clkdv_cnt <= 0;
      else
           clkdv_cnt <= clkdv_cnt + 1;

      if (clkdv_cnt < divide_type /2)
          clkdv_out <= 1'b1;
      else
         if ( (divide_type[0] == 1'b1) && dll_mode_type == 2'b00)
             clkdv_out <= #(period/4) 1'b0;
         else
            clkdv_out <= 1'b0;
    end

//
//determine_clkfx_divide_multiply
//
always @( rst_in or clkfx_multiply_drp or clkfx_divide_drp)
begin
    if (rst_in == 1 ) begin
        numerator = clkfx_multiply_drp;
        denominator = clkfx_divide_drp;
    end
end 
     
//
// generate fx output signal
//

always @(lock_period or period_fxtmp or denominator or numerator )
    if (lock_period == 1'b1) 
      period_fxavg = (period_fxtmp * denominator) / (numerator * 2);


always @(lock_period or period or denominator or numerator )
    if (lock_period == 1'b1) begin
       period_fx = (period * denominator) / (numerator * 2);
       remain_fx = (period * denominator) % (numerator * 2);
    end

always @(clkfx_out_avg or clkfx_out_ph)
  if (DFS_OSCILLATOR_MODE == "AVE_FREQ_LOCK")
     clkfx_out = clkfx_out_avg;