dcm_adv.v

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        end
    endcase

    case (DESKEW_ADJUST)
	"SOURCE_SYNCHRONOUS" : deskew_adjust_mode = 0;
	"SYSTEM_SYNCHRONOUS" : deskew_adjust_mode = 11;
	"0"		     : deskew_adjust_mode = 0;
	"1"		     : deskew_adjust_mode = 1;
	"2"		     : deskew_adjust_mode = 2;
	"3"		     : deskew_adjust_mode = 3;
	"4"		     : deskew_adjust_mode = 4;
	"5"		     : deskew_adjust_mode = 5;
	"6"		     : deskew_adjust_mode = 6;
	"7"		     : deskew_adjust_mode = 7;
	"8"		     : deskew_adjust_mode = 8;
	"9"		     : deskew_adjust_mode = 9;
	"10"		     : deskew_adjust_mode = 10;
	"11"		     : deskew_adjust_mode = 11;
	"12"		     : deskew_adjust_mode = 12;
	"13"		     : deskew_adjust_mode = 13;
	"14"		     : deskew_adjust_mode = 14;
	"15"		     : deskew_adjust_mode = 15;
        "16"                 : deskew_adjust_mode = 16;
        "17"                 : deskew_adjust_mode = 17;
        "18"                 : deskew_adjust_mode = 18;
        "19"                 : deskew_adjust_mode = 19;
        "20"                 : deskew_adjust_mode = 20;
        "21"                 : deskew_adjust_mode = 21;
        "22"                 : deskew_adjust_mode = 22;
        "23"                 : deskew_adjust_mode = 23;
        "24"                 : deskew_adjust_mode = 24;
        "25"                 : deskew_adjust_mode = 25;
        "26"                 : deskew_adjust_mode = 26;
        "27"                 : deskew_adjust_mode = 27;
        "28"                 : deskew_adjust_mode = 28;
        "29"                 : deskew_adjust_mode = 29;
        "30"                 : deskew_adjust_mode = 30;
        "31"                 : deskew_adjust_mode = 31;
	default : begin
	    $display("Attribute Syntax Error : The attribute DESKEW_ADJUST on DCM_ADV instance %m is set to %s.  Legal values for this attribute are SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or 0 ... 15.", DESKEW_ADJUST);
	    $finish;
	end
    endcase

    case (DFS_FREQUENCY_MODE)
	"HIGH" : dfs_mode_type_i = 1;
	"LOW"  : dfs_mode_type_i = 0;
	default : begin
	    $display(" Attribute Syntax Error : The attribute DFS_FREQUENCY_MODE on DCM_ADV instance %m is set to %s. Legal values for this attribute are HIGH or LOW.", DFS_FREQUENCY_MODE);
	    $finish;
	end
     endcase

    period_jitter = SIM_CLKIN_PERIOD_JITTER;
    cycle_jitter = SIM_CLKIN_CYCLE_JITTER;

    case (DLL_FREQUENCY_MODE)
	"HIGH" : dll_mode_type_i = 2'b11;
	"LOW"  : dll_mode_type_i = 2'b00;
	default : begin
	    $display("Attribute Syntax Error : The attribute DLL_FREQUENCY_MODE on DCM_ADV instance %m is set to %s.  Legal values for this attribute are HIGH or LOW.", DLL_FREQUENCY_MODE);
	    $finish;
	end
    endcase

    case (FACTORY_JF)
      16'hF0F0 : ;
      default : 
	    $display("Attribute Syntax Warning : The attribute FACTORY_JF on DCM_ADV instance %m is set to %h.  Legal value is F0F0.", FACTORY_JF);
    endcase

    case (DUTY_CYCLE_CORRECTION)
	"FALSE" : clk1x_type = 0;
	"TRUE"  : clk1x_type = 1;
	default : begin
	    $display("Attribute Syntax Error : The attribute DUTY_CYCLE_CORRECTION on DCM_ADV instance %m is set to %s.  Legal values for this attribute are TRUE or FALSE.", DUTY_CYCLE_CORRECTION);
	    $finish;
	end
    endcase

    case (STARTUP_WAIT)
	"FALSE" : ;
	"TRUE"  : ;
	default : begin
	    $display("Attribute Syntax Error : The attribute STARTUP_WAIT on DCM_ADV instance %m is set to %s.  Legal values for this attribute are TRUE or FALSE.", STARTUP_WAIT);
	    $finish;
	end
    endcase

    case (DCM_AUTOCALIBRATION)
        "FALSE" : ;
        "TRUE"  : ;
        default : begin
            $display("Attribute Syntax Error : The attribute DCM_AUTOCALIBRATION on DCM_ADV instance %m is set to %s.  Legal values for this attribute are TRUE or FALSE.", DCM_AUTOCALIBRATION);
            $finish;
        end
    endcase

        case (SIM_DEVICE)
                "VIRTEX5" : sim_device_type = 1;
                "VIRTEX4" : sim_device_type = 0;
                default : begin
                        $display("Attribute Syntax Error : The Attribute SIM_DEVICE on DCM_ADV instance %m is set to %s.  Legal values for this attribute are VIRTEX5 or VIRTEX4.", SIM_DEVICE);
                        $finish;
                end
        endcase

end


//
// input wire delays
//

      assign #100 LOCKED = locked_out_out;
      assign #100 PSDONE = psdone_out;
      assign #100 DO = do_out;
      assign #100 DRDY = drdy_out;
      assign clkin_in = CLKIN;
      assign clkfb_in = CLKFB;
      assign psclk_in = PSCLK;
      assign  psen_in = PSEN;
      assign psincdec_in = PSINCDEC;
      assign gsr_in = GSR;
      assign  rst_input = RST;
      assign daddr_in = DADDR;
      assign  di_in = DI;
      assign dwe_in = DWE;
      assign  den_in = DEN;
      assign  dclk_in = DCLK;

assign rst_in = rst_input;

dcm_adv_clock_divide_by_2 i_clock_divide_by_2 (clkin_in, clkin_type, clkin_div, rst_in);

dcm_adv_maximum_period_check #("CLKIN", MAXPERCLKIN) i_max_clkin (clkin_in, rst_in);
dcm_adv_maximum_period_check #("PSCLK", MAXPERPSCLK) i_max_psclk (psclk_in, rst_in);

dcm_adv_clock_lost i_clkin_lost (clkin_in, first_time_locked, clkin_lost_out, rst_in);
dcm_adv_clock_lost i_clkfx_lost (CLKFX, first_time_locked, clkfx_lost_out, rst_in);
dcm_adv_clock_lost i_clkfb_lost (CLKFB, first_time_locked, clkfb_lost_out, rst_in);


always @(clkin_div) 
    clkin_ps <= #(ps_delay) clkin_div;

always @(clkin_ps or lock_fb)
    clkin_fb =  clkin_ps & lock_fb;

always @(posedge clkin_fb or posedge chk_rst)
    if (chk_rst)
       clkin_chkin <= 0;
    else
       clkin_chkin <= 1;

always @(posedge clkfb_in or posedge chk_rst)
    if (chk_rst)
       clkfb_chkin <= 0;
    else
       clkfb_chkin <= 1;

    assign chk_rst = (rst_in==1 || clock_stopped==1 ) ? 1 : 0;
    assign chk_enable = (clkin_chkin == 1 && clkfb_chkin == 1 &&
                         lock_ps ==1 && lock_fb ==1 ) ? 1 : 0;

always @(posedge clkin_div or posedge rst_in)
  if (rst_in) begin
     period_div <= 0;
     clkin_div_edge <= 0;
   end
  else
 if ( clkin_div == 1) begin
    clkin_div_edge <= $time;
    if (($time - clkin_div_edge) <= (1.5 * period_div))
	period_div <= $time - clkin_div_edge;
    else if ((period_div == 0) && (clkin_div_edge != 0))
	period_div <= $time - clkin_div_edge;
 end


always @(posedge clkin_ps or posedge rst_in) 
  if (rst_in) begin
        period_ps <= 0;
        clkin_ps_edge <= 0;
  end
  else
  if (clkin_ps==1) begin
    clkin_ps_edge <= $time;
    if (($time - clkin_ps_edge) <= (1.5 * period_ps))
	period_ps <= $time - clkin_ps_edge;
    else if ((period_ps == 0) && (clkin_ps_edge != 0))
	period_ps <= $time - clkin_ps_edge;
   end

always @(posedge clkin_ps) begin
    lock_ps <= lock_period;
    lock_ps_dly <= lock_ps;
    lock_fb <= lock_ps_dly;
end

always @(period or fb_delay)
  if (fb_delay ==0)
    clkout_delay = 0;
  else
    clkout_delay = period - fb_delay;

//
// generate master reset signal
//

always @(posedge clkin_in) begin
    rst_reg[0] <= rst_input;
    rst_reg[1] <= rst_reg[0] & rst_input;
    rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst_input;
end

reg rst_tmp1, rst_tmp2;
initial
begin
rst_tmp1 = 0;
rst_tmp2 = 0;
rst_flag = 0;
end

always @(rst_input)
begin
   if (rst_input)
      rst_flag = 0;

   rst_tmp1 = rst_input;
   if (rst_tmp1 == 0 && rst_tmp2 == 1) begin
    if ((rst_reg[2] & rst_reg[1] & rst_reg[0]) == 0) begin
        rst_flag = 1;
	$display("Input Error : RST on instance %m must be asserted for 3 CLKIN clock cycles.");
     end
   end
   rst_tmp2 = rst_tmp1;
end

initial begin
    CLK0 = 0;
    CLK2X =0;
    CLK2X180 = 0;
    CLK90 = 0;
    CLK180 =0;
    CLK270 = 0;
    CLKDV = 0;
    CLKFX = 0;
    CLKFX180 =0;
    clk0_out = 0;
    clk2x_out = 0;
    clkdv_cnt = 0;
    clkdv_out = 0;
    clkfb_window = 0;
    clkfx_out = 0;
    clkfx_out_avg = 0;
    clkfx_out_ph = 0;
    clkin_div_edge = 0;
    clkin_period[0] = 0;
    clkin_period[1] = 0;
    clkin_period[2] = 0;
    period = 0;
    clkin_ps_edge = 0;
    clkin_window = 0;
    clkout_delay = 0;
    clock_stopped = 1;
    fb_delay  = 0;
    fb_delay_found = 0;
    lock_clkfb = 0;
    lock_clkin = 0;
    lock_delay = 0;
    lock_fb = 0;
    lock_out = 2'b00;
    lock_out1_neg = 0;
    lock_period = 0;
    lock_ps = 0;
    lock_ps_dly = 0;
    locked_out = 0;
    period = 0;
    period_div = 0;
    period_fx = 0;
    period_fxavg = 0;
    period_orig = 0;
    period_stop_ck = 0;
    period_ps = 0;
    delay_edge = 0;
    psdone_out = 0;
    ps_delay = 0;
    ps_lock = 0;
    inc_dec = 0;
    ps_overflow_out = 0;
    ps_delay_ps = 0;
    ps_delay_drp = 0;
    rst_reg = 3'b000;
    numerator = CLKFX_MULTIPLY;
    denominator = CLKFX_DIVIDE;
    clkfx_multiply_drp = CLKFX_MULTIPLY;
    clkfx_divide_drp = CLKFX_DIVIDE;
    clkfx_m_reg = CLKFX_MULTIPLY;
    clkfx_d_reg = CLKFX_DIVIDE;
    clkfx_md_reg = {clkfx_m_reg, clkfx_d_reg};
    gcd = 1;
    drdy_out = 0;
    do_out_drp = 16'h0000;
    do_out_drp1 = 16'h0000;
    do_out_s = 16'h0000;
    valid_daddr = 0;
    
    first_time_locked = 0;
    en_status = 0;
    drp_lock = 0;
    ps_drp = 0;
    ps_kick_off_cmd = 0;
    single_step_lock = 0;
    single_step_lock_tmp = 0;
    single_step_done = 0;
    ps_drp_lock = 0;
    ps_drp_lock_tmp = 0;
    clkin_chkin = 0;
    clkfb_chkin = 0;

    dfs_mode_reg = {13'bxxxxxxxxxxxxx, dfs_mode_type_i, 2'bxx};
    dll_mode_reg = {12'bxxxxxxxxxxxx, dll_mode_type_i, 2'bxx};
    clkin_div2_reg = {5'bxxxxx, clkin_type_i, 10'bxxxxxxxxxx};
    do_stat_en = 1;
end


   assign dfs_mode_type = dfs_mode_reg[2];
   assign dll_mode_type = dll_mode_reg[3:2];
   assign clkin_type = clkin_div2_reg[10];
//
// phase shift parameters
//

always @(posedge lock_period) begin
  if ((ps_type == 3'b000) || (ps_type == 3'b001) || (ps_type == 3'b011) || (ps_type == 3'b100))  begin
    if (PHASE_SHIFT > 0) begin
	if ((ps_in * period_orig / 256) > period_orig + FINE_SHIFT_RANGE) begin
            $display("Function Error : Instance %m Requested Phase Shift = PHASE_SHIFT * PERIOD / 256 = %d * %1.3f / 256 = %1.3f. This exceeds the FINE_SHIFT_RANGE of %1.3f ns.", PHASE_SHIFT, period_orig / 1000.0, PHASE_SHIFT * period_orig/ 256 / 1000.0, FINE_SHIFT_RANGE / 1000.0);
	      $finish;
	end
    end
    else if (PHASE_SHIFT < 0) begin
	if ((period_orig > FINE_SHIFT_RANGE) &&
	    ((ps_in * period_orig / 256) < period_orig - FINE_SHIFT_RANGE)) begin
            $display("Function Error : Instance %m Requested Phase Shift = PHASE_SHIFT * PERIOD / 256 = %d * %1.3f / 256 = %1.3f. This exceeds the FINE_SHIFT_RANGE of %1.3f ns.", PHASE_SHIFT, period_orig / 1000.0, -(PHASE_SHIFT) * period_orig / 256 / 1000.0, FINE_SHIFT_RANGE / 1000.0);
	      $finish;
	end
    end
  end
  else if (ps_type == 3'b101) begin
            if ((ps_in * tap_delay_step) > FINE_SHIFT_RANGE) begin
	    $display(" Phase shift Error : Allowed phase shift range on instance %m is between 0 to  %d. ", FINE_SHIFT_RANGE / tap_delay_step);
	      $finish;
            end
  end
end

always @(posedge lock_period_pulse or posedge rst_in or ps_delay_ps or ps_delay_drp or ps_in_ps
          or ps_in_psdrp) 
  if (rst_in) begin
     ps_delay <= 0;
     ps_in_curr <= ps_in;
  end
  else  if (lock_period_pulse) begin
     if ((ps_type == 3'b000) || (ps_type == 3'b001) || (ps_type == 3'b011) || (ps_type == 3'b100))
          ps_delay <= (ps_in * period_div / 256);
     else if (ps_type == 3'b101) 
          ps_delay <= ps_in * tap_delay_step;
  end
  else  begin
    if (((ps_type == 3'b011) || (ps_type == 3'b100) ) ) 
     begin
          ps_in_curr = ps_in_ps;
          ps_delay = (ps_in_ps * period_div / 256);
     end
    else if ((ps_type == 3'b101) && (ps_lock==1))
    begin
          ps_in_curr = ps_in_ps;
          ps_delay = ps_in_ps * tap_delay_step;
    end
    else if ((ps_type == 3'b101) && (ps_drp_lock==1))
    begin
          ps_in_curr = ps_in_psdrp;
          ps_delay = ps_delay_drp;
    end
  end
     



always @(posedge psclk_in or posedge rst_in) 
  if (rst_in) begin
    ps_in_ps <= ps_in;
    ps_overflow_out <= 0;
//    ps_delay_ps <= 0;
  end
  else begin
    if ((ps_type == 3'b011) || (ps_type == 3'b100) ) begin
	if (psen_in)
	    if (ps_lock == 1)
		  $display(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift.");
	    else
	    if (psincdec_in == 1) begin
		if (ps_in_ps == ps_max)
		    ps_overflow_out <= 1;
		else if (((ps_in_ps + 1) * period_orig / 256) > period_orig + FINE_SHIFT_RANGE)
		    ps_overflow_out <= 1;
		else begin
		    ps_in_ps <= ps_in_ps + 1;
		    ps_overflow_out <= 0;
		end
		ps_lock <= 1;
	    end
	    else if (psincdec_in == 0) begin
		if (ps_in_ps == ps_min)
		    ps_overflow_out <= 1;
		else if ((period_orig > FINE_SHIFT_RANGE) &&
		     (((ps_in_ps - 1) * period_orig / 256) < period_orig - FINE_SHIFT_RANGE))
		      ps_overflow_out <= 1;
		else begin
		    ps_in_ps <= ps_in_ps - 1;
		    ps_overflow_out <= 0;
		end