📄 sim_tb_top.v
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);
// Extra one clock pipelining for RDIMM address and
// control signals is implemented here (Implemented external to memory model)
always @( posedge ddr2_clk[0] ) begin
if ( ddr2_reset_n == 1'b0 ) begin
ddr2_ras_n_reg <= 1'b1;
ddr2_cas_n_reg <= 1'b1;
ddr2_we_n_reg <= 1'b1;
ddr2_cs_n_reg <= {CS_WIDTH{1'b1}};
ddr2_odt_reg <= 1'b0;
end
else begin
ddr2_address_reg <= #(CLK_PERIOD_NS/2) ddr2_address;
ddr2_ba_reg <= #(CLK_PERIOD_NS/2) ddr2_ba;
ddr2_ras_n_reg <= #(CLK_PERIOD_NS/2) ddr2_ras_n;
ddr2_cas_n_reg <= #(CLK_PERIOD_NS/2) ddr2_cas_n;
ddr2_we_n_reg <= #(CLK_PERIOD_NS/2) ddr2_we_n;
ddr2_cs_n_reg <= #(CLK_PERIOD_NS/2) ddr2_cs_n;
ddr2_odt_reg <= #(CLK_PERIOD_NS/2) ddr2_odt;
end
end
// to avoid tIS violations on CKE when reset is deasserted
always @( posedge ddr2_clk_n[0] )
if ( ddr2_reset_n == 1'b0 )
ddr2_cke_reg <= 1'b0;
else
ddr2_cke_reg <= #(CLK_PERIOD_NS) ddr2_cke;
//***************************************************************************
// Memory model instances
//***************************************************************************
genvar i;
generate
if (DEVICE_WIDTH == 16) begin
// if memory part is x16
if ( REG_ENABLE ) begin
// if the memory part is Registered DIMM
for(i = 0; i < DQS_WIDTH/2; i = i+1) begin
ddr2_model u_mem0
(
.ck (ddr2_clk[CLK_WIDTH*i/DQS_WIDTH]),
.ck_n (ddr2_clk_n[CLK_WIDTH*i/DQS_WIDTH]),
.cke (ddr2_cke_reg),
.cs_n (ddr2_cs_n_reg[CS_WIDTH*i/DQS_WIDTH]),
.ras_n (ddr2_ras_n_reg),
.cas_n (ddr2_cas_n_reg),
.we_n (ddr2_we_n_reg),
.dm_rdqs (ddr2_dm[(2*(i+1))-1 : i*2]),
.ba (ddr2_ba_reg),
.addr (ddr2_address_reg),
.dq (ddr2_dq[(16*(i+1))-1 : i*16]),
.dqs (ddr2_dqs[(2*(i+1))-1 : i*2]),
.dqs_n (ddr2_dqs_n[(2*(i+1))-1 : i*2]),
.rdqs_n (),
.odt (ddr2_odt_reg[ODT_WIDTH*i/DQS_WIDTH])
);
end
end
else begin
// if the memory part is component or unbuffered DIMM
if ( DQ_WIDTH%16 ) begin
// for the memory part x16, if the data width is not multiple
// of 16, memory models are instantiated for all data with x16
// memory model and except for MSB data. For the MSB data
// of 8 bits, all memory data, strobe and mask data signals are
// replicated to make it as x16 part. For example if the design
// is generated for data width of 72, memory model x16 parts
// instantiated for 4 times with data ranging from 0 to 63.
// For MSB data ranging from 64 to 71, one x16 memory model
// by replicating the 8-bit data twice and similarly
// the case with data mask and strobe.
for(i = 0; i < DQ_WIDTH/16 ; i = i+1) begin
ddr2_model u_mem0
(
.ck (ddr2_clk[i]),
.ck_n (ddr2_clk_n[i]),
.cke (ddr2_cke),
.cs_n (ddr2_cs_n[i]),
.ras_n (ddr2_ras_n),
.cas_n (ddr2_cas_n),
.we_n (ddr2_we_n),
.dm_rdqs (ddr2_dm[(2*(i+1))-1 : i*2]),
.ba (ddr2_ba),
.addr (ddr2_address),
.dq (ddr2_dq[(16*(i+1))-1 : i*16]),
.dqs (ddr2_dqs[(2*(i+1))-1 : i*2]),
.dqs_n (ddr2_dqs_n[(2*(i+1))-1 : i*2]),
.rdqs_n (),
.odt (ddr2_odt[i])
);
end
ddr2_model u_mem1
(
.ck (ddr2_clk[CLK_WIDTH-1]),
.ck_n (ddr2_clk_n[CLK_WIDTH-1]),
.cke (ddr2_cke),
.cs_n (ddr2_cs_n[CS_WIDTH-1]),
.ras_n (ddr2_ras_n),
.cas_n (ddr2_cas_n),
.we_n (ddr2_we_n),
.dm_rdqs ({ddr2_dm[DM_WIDTH - 1],
ddr2_dm[DM_WIDTH - 1]}),
.ba (ddr2_ba),
.addr (ddr2_address),
.dq ({ddr2_dq[DQ_WIDTH - 1 : DQ_WIDTH - 8],
ddr2_dq[DQ_WIDTH - 1 : DQ_WIDTH - 8]}),
.dqs ({ddr2_dqs[DQS_WIDTH - 1],
ddr2_dqs[DQS_WIDTH - 1]}),
.dqs_n ({ddr2_dqs_n[DQS_WIDTH - 1],
ddr2_dqs_n[DQS_WIDTH - 1]}),
.rdqs_n (),
.odt (ddr2_odt[ODT_WIDTH-1])
);
end
else begin
// if the data width is multiple of 16
for(i = 0; i < CS_WIDTH; i = i+1) begin
ddr2_model u_mem0
(
.ck (ddr2_clk[i]),
.ck_n (ddr2_clk_n[i]),
.cke (ddr2_cke),
.cs_n (ddr2_cs_n[i]),
.ras_n (ddr2_ras_n),
.cas_n (ddr2_cas_n),
.we_n (ddr2_we_n),
.dm_rdqs (ddr2_dm[(2*(i+1))-1 : i*2]),
.ba (ddr2_ba),
.addr (ddr2_address),
.dq (ddr2_dq[(16*(i+1))-1 : i*16]),
.dqs (ddr2_dqs[(2*(i+1))-1 : i*2]),
.dqs_n (ddr2_dqs_n[(2*(i+1))-1 : i*2]),
.rdqs_n (),
.odt (ddr2_odt[i])
);
end
end
end
end else
if (DEVICE_WIDTH == 8) begin
// if the memory part is x8
if ( REG_ENABLE ) begin
// if the memory part is Registered DIMM
for(i = 0; i < DQ_WIDTH/DQ_PER_DQS; i = i+1) begin
ddr2_model u_mem0
(
.ck (ddr2_clk[CLK_WIDTH*i/DQS_WIDTH]),
.ck_n (ddr2_clk_n[CLK_WIDTH*i/DQS_WIDTH]),
.cke (ddr2_cke_reg),
.cs_n (ddr2_cs_n_reg[CS_WIDTH*i/DQS_WIDTH]),
.ras_n (ddr2_ras_n_reg),
.cas_n (ddr2_cas_n_reg),
.we_n (ddr2_we_n_reg),
.dm_rdqs (ddr2_dm[i]),
.ba (ddr2_ba_reg),
.addr (ddr2_address_reg),
.dq (ddr2_dq[(8*(i+1))-1 : i*8]),
.dqs (ddr2_dqs[i]),
.dqs_n (ddr2_dqs_n[i]),
.rdqs_n (),
.odt (ddr2_odt_reg[ODT_WIDTH*i/DQS_WIDTH])
);
end
end
else begin
// if the memory part is component or unbuffered DIMM
for(i = 0; i < CS_WIDTH; i = i+1) begin
ddr2_model u_mem0
(
.ck (ddr2_clk[i]),
.ck_n (ddr2_clk_n[i]),
.cke (ddr2_cke),
.cs_n (ddr2_cs_n[i]),
.ras_n (ddr2_ras_n),
.cas_n (ddr2_cas_n),
.we_n (ddr2_we_n),
.dm_rdqs (ddr2_dm[i]),
.ba (ddr2_ba),
.addr (ddr2_address),
.dq (ddr2_dq[(8*(i+1))-1 : i*8]),
.dqs (ddr2_dqs[i]),
.dqs_n (ddr2_dqs_n[i]),
.rdqs_n (),
.odt (ddr2_odt[i])
);
end
end
end else
if (DEVICE_WIDTH == 4) begin
// if the memory part is x4
if ( REG_ENABLE ) begin
// if the memory part is Registered DIMM
for(i = 0; i < DQS_WIDTH; i = i+1) begin
ddr2_model u_mem0
(
.ck (ddr2_clk[CLK_WIDTH*i/DQS_WIDTH]),
.ck_n (ddr2_clk_n[CLK_WIDTH*i/DQS_WIDTH]),
.cke (ddr2_cke_reg),
.cs_n (ddr2_cs_n_reg[CS_WIDTH*i/DQS_WIDTH]),
.ras_n (ddr2_ras_n_reg),
.cas_n (ddr2_cas_n_reg),
.we_n (ddr2_we_n_reg),
.dm_rdqs (ddr2_dm[i]),
.ba (ddr2_ba_reg),
.addr (ddr2_address_reg),
.dq (ddr2_dq[(4*(i+1))-1 : i*4]),
.dqs (ddr2_dqs[i]),
.dqs_n (ddr2_dqs_n[i]),
.rdqs_n (),
.odt (ddr2_odt_reg[ODT_WIDTH*i/DQS_WIDTH])
);
end
end
else begin
// if the memory part is component or unbuffered DIMM
for(i = 0; i < CS_WIDTH; i = i+1) begin
ddr2_model u_mem0
(
.ck (ddr2_clk[i]),
.ck_n (ddr2_clk_n[i]),
.cke (ddr2_cke),
.cs_n (ddr2_cs_n[i]),
.ras_n (ddr2_ras_n),
.cas_n (ddr2_cas_n),
.we_n (ddr2_we_n),
.dm_rdqs (ddr2_dm[i]),
.ba (ddr2_ba),
.addr (ddr2_address),
.dq (ddr2_dq[(4*(i+1))-1 : i*4]),
.dqs (ddr2_dqs[i]),
.dqs_n (ddr2_dqs_n[i]),
.rdqs_n (),
.odt (ddr2_odt[i])
);
end
end
end
endgenerate
endmodule
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