sim_tb_top.v

DDR2源代码 DDR2源代码 DDR2源代码

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//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : 2.1
//  \   \        Application        : MIG
//  /   /        Filename           : sim_tb_top.v
// /___/   /\    Date Last Modified : $Date: 2008/01/09 15:43:36 $
// \   \  /  \   Date Created       : Mon May 14 2007
//  \___\/\___\
//
// Device      : Virtex-5
// Design Name : DDR2
// Purpose     : This is the simulation testbench which is used to verify the
//               design. The basic clocks and resets to the interface are
//               generated here. This also connects the memory interface to the
//               memory model.
// Reference:
// Revision History:
//*****************************************************************************

`timescale 1ns / 1ps

module sim_tb_top;

  // memory controller parameters
   parameter BANK_WIDTH       = 2;      // # of memory bank addr bits
   parameter CKE_WIDTH        = 1;      // # of memory clock enable outputs
   parameter CLK_WIDTH        = 1;      // # of clock outputs
   parameter COL_WIDTH        = 9;     // # of memory column bits
   parameter CS_NUM           = 1;      // # of separate memory chip selects
   parameter CS_WIDTH         = 1;      // # of total memory chip selects
   parameter CS_BITS          = 0;      // set to log2(CS_NUM) (rounded up)
   parameter DM_WIDTH         = 2;      // # of data mask bits
   parameter DQ_WIDTH         = 16;      // # of data width
   parameter DQ_PER_DQS       = 8;      // # of DQ data bits per strobe
   parameter DQS_WIDTH        = 2;      // # of DQS strobes
   parameter DQ_BITS          = 4;      // set to log2(DQS_WIDTH*DQ_PER_DQS)
   parameter DQS_BITS         = 1;      // set to log2(DQS_WIDTH)
   parameter ODT_WIDTH        = 1;      // # of memory on-die term enables
   parameter ROW_WIDTH        = 13;     // # of memory row & # of addr bits
   parameter APPDATA_WIDTH    = 32;     // # of usr read/write data bus bits
   parameter ADDITIVE_LAT     = 0;      // additive write latency
   parameter BURST_LEN        = 4;      // burst length (in double words)
   parameter BURST_TYPE       = 0;      // burst type (=0 seq; =1 interlved)
   parameter CAS_LAT          = 5;      // CAS latency
   parameter ECC_ENABLE       = 0;      // enable ECC (=1 enable)
   parameter MULTI_BANK_EN    = 1;      // enable bank management
   parameter TWO_T_TIME_EN    = 0;      // 2t timing for unbuffered dimms
   parameter ODT_TYPE         = 1;      // ODT (=0(none),=1(75),=2(150),=3(50))
   parameter REDUCE_DRV       = 0;      // reduced strength mem I/O (=1 yes)
   parameter REG_ENABLE       = 0;      // registered addr/ctrl (=1 yes)
   parameter TREFI_NS         = 7800;   // auto refresh interval (ns)
   parameter TRAS             = 40000;  // active->precharge delay
   parameter TRCD             = 15000;  // active->read/write delay
   parameter TRFC             = 75000;  // ref->ref, ref->active delay
   parameter TRP              = 15000;  // precharge->command delay
   parameter TRTP             = 7500;   // read->precharge delay
   parameter TWR              = 15000;  // used to determine wr->prech
   parameter TWTR             = 7500;   // write->read delay
   parameter SIM_ONLY         = 1;      // = 0 to allow power up delay
   parameter DEBUG_EN         = 0;      // Enable debug signals/controls
   parameter RST_ACT_LOW      = 1;      // =1 for active low reset, =0 for active high
   parameter DLL_FREQ_MODE    = "HIGH"; // DCM Frequency range
   parameter CLK_PERIOD       = 3333;   // Core/Mem clk period (in ps)

   localparam DEVICE_WIDTH    = 16;      // Memory device data width
   localparam real CLK_PERIOD_NS   = CLK_PERIOD / 1000.0;
   localparam real TCYC_200        = 5.0;
   localparam real TPROP_DQS       = 0.00;
   localparam real TPROP_PCB_CTRL  = 0.00;
   localparam real TPROP_PCB_DATA  = 0.00;

   reg                           sys_clk;
   wire                          sys_clk_n;
   wire                          sys_clk_p;
   reg                           sys_clk200;
   wire                          clk200_n;
   wire                          clk200_p;
   reg                           sys_rst_n;

   wire [DQ_WIDTH-1:0]           #(TPROP_PCB_DATA) ddr2_dq;
   wire [DQS_WIDTH-1:0]          #(TPROP_PCB_DATA) ddr2_dqs;
   wire [DQS_WIDTH-1:0]          #(TPROP_PCB_DATA) ddr2_dqs_n;
   wire [DM_WIDTH-1:0]           #(TPROP_PCB_DATA) ddr2_dm;
   wire [CLK_WIDTH-1:0]          #(TPROP_PCB_CTRL) ddr2_clk;
   wire [CLK_WIDTH-1:0]          #(TPROP_PCB_CTRL) ddr2_clk_n;
   wire [ROW_WIDTH-1:0]          #(TPROP_PCB_CTRL) ddr2_address;
   wire [BANK_WIDTH-1:0]         #(TPROP_PCB_CTRL) ddr2_ba;
   wire #(TPROP_PCB_CTRL)        ddr2_ras_n;
   wire #(TPROP_PCB_CTRL)        ddr2_cas_n;
   wire #(TPROP_PCB_CTRL)        ddr2_we_n;
   wire [CS_WIDTH-1:0]           #(TPROP_PCB_CTRL) ddr2_cs_n;
   wire [CKE_WIDTH-1:0]          #(TPROP_PCB_CTRL) ddr2_cke;
   wire [ODT_WIDTH-1:0]          #(TPROP_PCB_CTRL) ddr2_odt;
   wire                          error;
   wire                          phy_init_done;
   

   // Only RDIMM memory parts support the reset signal, 
   // hence the ddr2_reset_n signal can be ignored for other memory parts
   wire                          ddr2_reset_n;
   reg [ROW_WIDTH-1:0]           ddr2_address_reg;
   reg [BANK_WIDTH-1:0]          ddr2_ba_reg;
   reg [CKE_WIDTH-1:0]           ddr2_cke_reg;
   reg                           ddr2_ras_n_reg;
   reg                           ddr2_cas_n_reg;
   reg                           ddr2_we_n_reg;
   reg [CS_WIDTH-1:0]            ddr2_cs_n_reg;
   reg [ODT_WIDTH-1:0]           ddr2_odt_reg;
   
   //***************************************************************************
   // Clock generation and reset
   //***************************************************************************

   initial
     sys_clk = 1'b0;
   always
     sys_clk = #(CLK_PERIOD_NS/2) ~sys_clk;

   assign                sys_clk_p = sys_clk;
   assign                sys_clk_n = ~sys_clk;

   initial
     sys_clk200 = 1'b0;
   always
     sys_clk200 = #(TCYC_200/2) ~sys_clk200;

   assign                clk200_p = sys_clk200;
   assign                clk200_n = ~sys_clk200;

   initial begin
      sys_rst_n = 1'b0;
      #200;
      sys_rst_n = 1'b1;
   end
   
   //***************************************************************************
   // FPGA memory controller
   //***************************************************************************

   ddr2_sdram #
     (
      .BANK_WIDTH     (BANK_WIDTH),
      .CKE_WIDTH      (CKE_WIDTH),
      .CLK_WIDTH      (CLK_WIDTH),
      .COL_WIDTH      (COL_WIDTH),
      .CS_NUM         (CS_NUM),
      .CS_WIDTH       (CS_WIDTH),
      .CS_BITS        (CS_BITS),
      .DM_WIDTH       (DM_WIDTH),
      .DQ_WIDTH       (DQ_WIDTH),
      .DQ_PER_DQS     (DQ_PER_DQS),
      .DQ_BITS        (DQ_BITS),
      .DQS_WIDTH      (DQS_WIDTH),
      .DQS_BITS       (DQS_BITS),
      .ODT_WIDTH      (ODT_WIDTH),
      .ROW_WIDTH      (ROW_WIDTH),
      .APPDATA_WIDTH  (APPDATA_WIDTH),
      .ADDITIVE_LAT   (ADDITIVE_LAT),
      .BURST_LEN      (BURST_LEN),
      .BURST_TYPE     (BURST_TYPE),
      .CAS_LAT        (CAS_LAT),
      .ECC_ENABLE     (ECC_ENABLE),
      .MULTI_BANK_EN  (MULTI_BANK_EN),
      .ODT_TYPE       (ODT_TYPE),
      .REDUCE_DRV     (REDUCE_DRV),
      .REG_ENABLE     (REG_ENABLE),
      .TREFI_NS       (TREFI_NS),
      .TRAS           (TRAS),
      .TRCD           (TRCD),
      .TRFC           (TRFC),
      .TRP            (TRP),
      .TRTP           (TRTP),
      .TWR            (TWR),
      .TWTR           (TWTR),
      .SIM_ONLY       (SIM_ONLY),
      .RST_ACT_LOW    (RST_ACT_LOW),
      .DLL_FREQ_MODE  (DLL_FREQ_MODE),
      .CLK_PERIOD     (CLK_PERIOD)
      )
   u_mem_controller
     (
      .sys_clk_p         (sys_clk_p),
      .sys_clk_n         (sys_clk_n),
      .clk200_p          (clk200_p),
      .clk200_n          (clk200_n),
      .sys_rst_n         (sys_rst_n),
      .ddr2_ras_n        (ddr2_ras_n),
      .ddr2_cas_n        (ddr2_cas_n),
      .ddr2_we_n         (ddr2_we_n),
      .ddr2_cs_n         (ddr2_cs_n),
      .ddr2_cke          (ddr2_cke),
      .ddr2_odt          (ddr2_odt),
      .ddr2_dm           (ddr2_dm),
      .ddr2_dq           (ddr2_dq),
      .ddr2_dqs          (ddr2_dqs),
      .ddr2_dqs_n        (ddr2_dqs_n),
      .ddr2_ck           (ddr2_clk),
      .ddr2_ck_n         (ddr2_clk_n),
      .ddr2_ba           (ddr2_ba),
      .ddr2_a            (ddr2_address),
      .error                (error),
      
      
      .phy_init_done     (phy_init_done)