phy_init.v

DDR2源代码 DDR2源代码 DDR2源代码

     ) /* synthesis syn_preserve=1 */
       /* synthesis syn_replicate = 0 */;

  //synthesis translate_off
  always @(posedge calib_done[0])
      $display ("First Stage Calibration completed at time %t", $time);

  always @(posedge calib_done[1])
    $display ("Second Stage Calibration completed at time %t", $time);

  always @(posedge calib_done[2]) begin
    $display ("Third Stage Calibration completed at time %t", $time);
  end

  always @(posedge calib_done[3]) begin
    $display ("Fourth Stage Calibration completed at time %t", $time);
    $display ("Calibration completed at time %t", $time);
  end
  //synthesis translate_on

  always @(posedge clkdiv0) begin
    if ((init_cnt_r >= INIT_CNTR_DEEP_MEM))begin
       init_done_r <= 1'b1;
    end else
       init_done_r <= 1'b0;
  end

  //*****************************************************************

  always @(posedge clkdiv0)
    if (rstdiv0) begin
      init_state_r  <= INIT_IDLE;
      init_state_r1 <= INIT_IDLE;
      init_state_r2 <= INIT_IDLE;
      calib_done_r  <= 4'b0000;
    end else begin
      init_state_r  <= init_next_state;
      init_state_r1 <= init_state_r;
      init_state_r2 <= init_state_r1;
      calib_done_r  <= calib_done; // register for timing
    end

  always @(*) begin
    init_next_state = init_state_r;
    (* full_case, parallel_case *) case (init_state_r)
      INIT_IDLE: begin
        if (done_200us_r) begin
          (* parallel_case *) case (init_cnt_r)
            INIT_CNTR_INIT:
              init_next_state = INIT_CNT_200;
            INIT_CNTR_PRECH_1:
              init_next_state = INIT_PRECHARGE;
            INIT_CNTR_EMR2_INIT:
              init_next_state = INIT_LOAD_MODE; // EMR(2)
            INIT_CNTR_EMR3_INIT:
              init_next_state = INIT_LOAD_MODE; // EMR(3);
            INIT_CNTR_EMR_EN_DLL:
              init_next_state = INIT_LOAD_MODE; // EMR, enable DLL
            INIT_CNTR_MR_RST_DLL:
              init_next_state = INIT_LOAD_MODE; // MR, reset DLL
            INIT_CNTR_CNT_200_WAIT:begin
              if(DDR_TYPE == DDR3)
                 init_next_state = INIT_ZQCL; // DDR3
              else
                // Wait 200cc after reset DLL
                init_next_state = INIT_CNT_200;
            end
            INIT_CNTR_PRECH_2:
              init_next_state = INIT_PRECHARGE;
            INIT_CNTR_AR_1:
              init_next_state = INIT_AUTO_REFRESH;
            INIT_CNTR_AR_2:
              init_next_state = INIT_AUTO_REFRESH;
            INIT_CNTR_MR_ACT_DLL:
              init_next_state = INIT_LOAD_MODE; // MR, unreset DLL
            INIT_CNTR_EMR_DEF_OCD:
              init_next_state = INIT_LOAD_MODE; // EMR, OCD default
            INIT_CNTR_EMR_EXIT_OCD:
              init_next_state = INIT_LOAD_MODE; // EMR, enable OCD exit
            INIT_CNTR_DEEP_MEM: begin
               if ((chip_cnt_r < CS_NUM-1))
                  init_next_state = INIT_DEEP_MEMORY_ST;
              else if (cnt_200_cycle_done_r)
                init_next_state = INIT_DUMMY_ACTIVE;
              else
                init_next_state = INIT_IDLE;
            end
            INIT_CNTR_PRECH_3:
              init_next_state = INIT_PRECHARGE;
            INIT_CNTR_DONE:
              init_next_state = INIT_IDLE;
            default :
              init_next_state = INIT_IDLE;
          endcase
        end
      end
      INIT_CNT_200:
        init_next_state = INIT_CNT_200_WAIT;
      INIT_CNT_200_WAIT:
        if (cnt_200_cycle_done_r)
          init_next_state = INIT_IDLE;
      INIT_PRECHARGE:
        init_next_state = INIT_PRECHARGE_WAIT;
      INIT_PRECHARGE_WAIT:
        if (cnt_cmd_ok_r)begin
          if (init_done_r && (!(&calib_done_r)))
            init_next_state = INIT_AUTO_REFRESH;
          else
            init_next_state = INIT_IDLE;
        end
      INIT_ZQCL:
        init_next_state = INIT_WAIT_DLLK_ZQINIT;
      INIT_WAIT_DLLK_ZQINIT:
        if (cnt_200_cycle_done_r)
          init_next_state = INIT_IDLE;
      INIT_LOAD_MODE:
        init_next_state = INIT_MODE_REGISTER_WAIT;
      INIT_MODE_REGISTER_WAIT:
        if (cnt_cmd_ok_r)
          init_next_state = INIT_IDLE;
      INIT_AUTO_REFRESH:
        init_next_state = INIT_AUTO_REFRESH_WAIT;
      INIT_AUTO_REFRESH_WAIT:
        if (cnt_cmd_ok_r)begin
          if(init_done_r)
            init_next_state = INIT_DUMMY_ACTIVE;
          else
            init_next_state = INIT_IDLE;
        end
      INIT_DEEP_MEMORY_ST:
        init_next_state = INIT_IDLE;
      // single row activate. All subsequent calibration writes and
      // read will take place in this row
      INIT_DUMMY_ACTIVE:
        init_next_state = INIT_DUMMY_ACTIVE_WAIT;
      INIT_DUMMY_ACTIVE_WAIT:
        if (cnt_cmd_ok_r)begin
          if (~calib_done_r[0]) begin
            // if returning to stg1 after refresh, don't need to write
            if (cal1_started_r)
              init_next_state = INIT_CAL1_READ;
            // if first entering stg1, need to write training pattern
            else
              init_next_state = INIT_CAL1_WRITE;
          end else if (~calib_done[1]) begin
            if (cal2_started_r)
              init_next_state = INIT_CAL2_READ;
            else
              init_next_state = INIT_CAL2_WRITE;
          end else if (~calib_done_r[2])
             init_next_state = INIT_CAL3_WRITE;
          else
            init_next_state = INIT_CAL4_READ;
        end
      // Stage 1 calibration (write and continuous read)
      INIT_CAL1_WRITE:
        if (burst_addr_r == 2'b10)
          init_next_state = INIT_CAL1_WRITE_READ;
      INIT_CAL1_WRITE_READ:
        if (cnt_cmd_ok_r)
          init_next_state = INIT_CAL1_READ;
      INIT_CAL1_READ:
        // Stage 1 requires inter-stage auto-refresh
        if (calib_done_r[0] || refresh_req)
          init_next_state = INIT_CAL1_READ_WAIT;
      INIT_CAL1_READ_WAIT:
        if (cnt_cmd_ok_r)
          init_next_state = INIT_CALIB_REF;
      // Stage 2 calibration (write and continuous read)
      INIT_CAL2_WRITE:
        if (burst_addr_r == 2'b10)
          init_next_state = INIT_CAL2_WRITE_READ;
      INIT_CAL2_WRITE_READ:
        if (cnt_cmd_ok_r)
          init_next_state = INIT_CAL2_READ;
      INIT_CAL2_READ:
        // Stage 2 requires inter-stage auto-refresh
        if (calib_done_r[1] || refresh_req)
          init_next_state = INIT_CAL2_READ_WAIT;
      INIT_CAL2_READ_WAIT:
        if(cnt_cmd_ok_r)
          init_next_state = INIT_CALIB_REF;
      // Stage 3 calibration (write and continuous read)
      INIT_CAL3_WRITE:
        if (burst_addr_r == 2'b10)
          init_next_state = INIT_CAL3_WRITE_READ;
      INIT_CAL3_WRITE_READ:
        if (cnt_cmd_ok_r)
          init_next_state = INIT_CAL3_READ;
      INIT_CAL3_READ:
        if (burst_addr_r == 2'b10)
          init_next_state = INIT_CAL3_READ_WAIT;
      INIT_CAL3_READ_WAIT: begin
        if (cnt_rd_ok_r)
          if (calib_done_r[2]) begin
            init_next_state = INIT_CALIB_REF;
          end else
            init_next_state = INIT_CAL3_READ;
      end
      // Stage 4 calibration (continuous read only, same pattern as stage 3)
      // only used if DQS_GATE supported
      INIT_CAL4_READ:
        if (burst_addr_r == 2'b10)
          init_next_state = INIT_CAL4_READ_WAIT;
      INIT_CAL4_READ_WAIT: begin
        if (cnt_rd_ok_r)
          // Stage 4 requires inter-stage auto-refresh
          if (calib_done_r[3] || refresh_req)
            init_next_state = INIT_PRECHARGE;
          else
            init_next_state = INIT_CAL4_READ;
      end
      INIT_CALIB_REF:
        init_next_state = INIT_PRECHARGE;
    endcase
  end

  //***************************************************************************
  // Memory control/address
  //***************************************************************************

  always @(posedge clkdiv0)
    if ((init_state_r == INIT_DUMMY_ACTIVE) ||
        (init_state_r == INIT_PRECHARGE) ||
        (init_state_r == INIT_LOAD_MODE) ||
        (init_state_r == INIT_AUTO_REFRESH)) begin
      ddr_ras_n_r <= 1'b0;
    end else begin
      ddr_ras_n_r <= 1'b1;
    end

  always @(posedge clkdiv0)
    if ((init_state_r == INIT_LOAD_MODE) ||
        (init_state_r == INIT_AUTO_REFRESH) ||
        (cal_write_read && (burst_cnt_r == 2'b00))) begin
      ddr_cas_n_r <= 1'b0;
    end else begin
      ddr_cas_n_r <= 1'b1;
    end

  always @(posedge clkdiv0)
    if ((init_state_r == INIT_LOAD_MODE) ||
        (init_state_r == INIT_PRECHARGE) ||
        (init_state_r == INIT_ZQCL) ||
        (cal_write && (burst_cnt_r == 2'b00)))begin
      ddr_we_n_r <= 1'b0;
    end else begin
      ddr_we_n_r <= 1'b1;
    end

  //*****************************************************************
  // memory address during init
  //*****************************************************************

  always @(posedge clkdiv0) begin
    if ((init_state_r == INIT_PRECHARGE)
        || (init_state_r == INIT_ZQCL))begin
      // Precharge all - set A10 = 1
      ddr_addr_r <= {ROW_WIDTH{1'b0}};
      ddr_addr_r[10] <= 1'b1;
      ddr_ba_r <= {BANK_WIDTH{1'b0}};
    end else if (init_state_r == INIT_LOAD_MODE) begin
      ddr_ba_r <= {BANK_WIDTH{1'b0}};
      ddr_addr_r <= {ROW_WIDTH{1'b0}};
      case (init_cnt_r)
        // EMR (2)
        INIT_CNTR_EMR2_INIT: begin
          ddr_ba_r[1:0] <= 2'b10;
          ddr_addr_r    <= {ROW_WIDTH{1'b0}};
        end
        // EMR (3)
        INIT_CNTR_EMR3_INIT: begin
          ddr_ba_r[1:0] <= 2'b11;
          if(DDR_TYPE == DDR3)
            ddr_addr_r    <= load_mode_reg3[ROW_WIDTH-1:0];
          else
            ddr_addr_r    <= {ROW_WIDTH{1'b0}};
        end
        // EMR write - A0 = 0 for DLL enable
        INIT_CNTR_EMR_EN_DLL: begin
          ddr_ba_r[1:0] <= 2'b01;
          if(DDR_TYPE == DDR3)
            ddr_addr_r <= load_mode_reg1[ROW_WIDTH-1:0];
          else
            ddr_addr_r <= ext_mode_reg[ROW_WIDTH-1:0];
        end
        // MR write, reset DLL (A8=1)
        INIT_CNTR_MR_RST_DLL: begin
          if(DDR_TYPE == DDR3)
            ddr_addr_r <= load_mode_reg0[ROW_WIDTH-1:0];
          else
            ddr_addr_r <= load_mode_reg[ROW_WIDTH-1:0];
          ddr_ba_r[1:0] <= 2'b00;
          ddr_addr_r[8] <= 1'b1;
        end
        // MR write, unreset DLL (A8=0)
        INIT_CNTR_MR_ACT_DLL: begin
          ddr_ba_r[1:0] <= 2'b00;
          ddr_addr_r <= load_mode_reg[ROW_WIDTH-1:0];
        end
        // EMR write, OCD default state
        INIT_CNTR_EMR_DEF_OCD: begin
          ddr_ba_r[1:0] <= 2'b01;
          ddr_addr_r <= ext_mode_reg[ROW_WIDTH-1:0];
          ddr_addr_r[9:7] <= 3'b111;
        end
        // EMR write - OCD exit
        INIT_CNTR_EMR_EXIT_OCD: begin
          ddr_ba_r[1:0] <= 2'b01;
          ddr_addr_r <= ext_mode_reg[ROW_WIDTH-1:0];
        end
        default: begin
          ddr_ba_r <= {BANK_WIDTH{1'bx}};
          ddr_addr_r <= {ROW_WIDTH{1'bx}};
        end
      endcase
    end else if (cal_write_read) begin
      // when writing or reading for Stages 2-4, since training pattern is
      // either 4 (stage 2) or 8 (stage 3-4) long, if BURST LEN < 8, then
      // need to issue multiple bursts to read entire training pattern
      ddr_addr_r[ROW_WIDTH-1:3] <= {ROW_WIDTH-4{1'b0}};
      ddr_addr_r[2:0]           <= {burst_addr_r, 1'b0};
      ddr_ba_r                  <= {BANK_WIDTH-1{1'b0}};
    end else if (init_state_r == INIT_DUMMY_ACTIVE) begin
      // all calibration writing read takes place in row 0x0 only
      ddr_ba_r   <= {BANK_WIDTH{1'b0}};
      ddr_addr_r <= {ROW_WIDTH{1'b0}};
    end else begin
      // otherwise, cry me a river
      ddr_ba_r   <= {BANK_WIDTH{1'bx}};
      ddr_addr_r <= {ROW_WIDTH{1'bx}};
    end
  end

  // Keep CKE asserted after initial power-on delay
  always @(posedge clkdiv0)
    ddr_cke_r <= {CKE_WIDTH{done_200us_r}};

  // register commands to memory. Two clock cycle delay from state -> output
  always @(posedge clk0) begin
    ddr_addr_r1   <= ddr_addr_r;
    ddr_ba_r1     <= ddr_ba_r;
    ddr_cas_n_r1  <= ddr_cas_n_r;
    ddr_ras_n_r1  <= ddr_ras_n_r;
    ddr_we_n_r1   <= ddr_we_n_r;
    ddr_cs_n_r1   <= ddr_cs_n_r;
  end // always @ (posedge clk0)

  // logic to toggle chip select. The chip_select is
  // clocked of clkdiv0 and will be asserted for
  // two clock cycles.
   always @(posedge clk0) begin
      if(rst0)
        ddr_cs_disable_r <= {CS_NUM{1'b0}};
      else begin
         if(ddr_cs_disable_r[chip_cnt_r])
            ddr_cs_disable_r[chip_cnt_r] <= 1'b0;
         else begin
            if(TWO_T_TIME_EN)
               ddr_cs_disable_r[chip_cnt_r] <= ~ddr_cs_n_r1[chip_cnt_r];
            else
               ddr_cs_disable_r[chip_cnt_r] <= ~ddr_cs_n_r[chip_cnt_r];
         end
       end
   end


  assign phy_init_addr      = ddr_addr_r;
  assign phy_init_ba        = ddr_ba_r;
  assign phy_init_cas_n     = ddr_cas_n_r;
  assign phy_init_cke       = ddr_cke_r;
  assign phy_init_ras_n     = ddr_ras_n_r;
  assign phy_init_we_n      = ddr_we_n_r;
  assign phy_init_cs_n      = (TWO_T_TIME_EN) ?
                              ddr_cs_n_r1 | ddr_cs_disable_r
                              : ddr_cs_n_r| ddr_cs_disable_r;

endmodule