phy_init.v

DDR2源代码 DDR2源代码 DDR2源代码

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//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 2.1
//  \   \         Application: MIG
//  /   /         Filename: phy_init.v
// /___/   /\     Date Last Modified: $Date: 2007/12/07 02:31:14 $
// \   \  /  \    Date Created: Thu Aug 24 2006
//  \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
//Reference:
//   This module is the intialization control logic of the memory interface.
//   All commands are issued from here acoording to the burst, CAS Latency and
//   the user commands.
//Revision History:
//*****************************************************************************

`timescale 1ns/1ps

module phy_init #
  (
   // Following parameters are for 72-bit RDIMM design (for ML561 Reference 
   // board design). Actual values may be different. Actual parameters values 
   // are passed from design top module ddr2_sdram module. Please refer to
   // the ddr2_sdram module for actual values.
   parameter BANK_WIDTH    = 2,
   parameter CKE_WIDTH     = 1,
   parameter COL_WIDTH     = 10,
   parameter CS_NUM        = 1,
   parameter DQ_WIDTH      = 72,
   parameter ODT_WIDTH     = 1,
   parameter ROW_WIDTH     = 14,
   parameter ADDITIVE_LAT  = 0,
   parameter BURST_LEN     = 4,
   parameter TWO_T_TIME_EN = 0,
   parameter BURST_TYPE    = 0,
   parameter CAS_LAT       = 5,
   parameter ODT_TYPE      = 1,
   parameter REDUCE_DRV    = 0,
   parameter REG_ENABLE    = 1,
   parameter DDR_TYPE      = 1,
   parameter SIM_ONLY      = 0
   )
  (
   input                                   clk0,
   input                                   clkdiv0,
   input                                   rst0,
   input                                   rstdiv0,
   input [3:0]                             calib_done,
   input                                   ctrl_ref_flag,
   input                                   calib_ref_req,
   output reg [3:0]                        calib_start,
   output reg                              calib_ref_done,
   output reg                              phy_init_wren,
   output reg                              phy_init_rden,
   output [ROW_WIDTH-1:0]                  phy_init_addr,
   output [BANK_WIDTH-1:0]                 phy_init_ba,
   output                                  phy_init_ras_n,
   output                                  phy_init_cas_n,
   output                                  phy_init_we_n,
   output [CS_NUM-1:0]                     phy_init_cs_n,
   output [CKE_WIDTH-1:0]                  phy_init_cke,
   output reg                              phy_init_done,
   output                                  phy_init_data_sel
   );

  // time to wait between consecutive commands in PHY_INIT - this is a
  // generic number, and must be large enough to account for worst case
  // timing parameter (tRFC - refresh-to-active) across all memory speed
  // grades and operating frequencies. Expressed in CLKDIV clock cycles.
  localparam  CNTNEXT_CMD = 7'b1111111;
  // time to wait between read and read or precharge for stage 3 & 4
  // the larger CNTNEXT_CMD can also be used, use smaller number to
  // speed up calibration - avoid tRAS violation, and speeds up simulation
  localparam  CNTNEXT_RD  = 4'b1111;

  localparam  INIT_CAL1_READ            = 5'h00;
  localparam  INIT_CAL2_READ            = 5'h01;
  localparam  INIT_CAL3_READ            = 5'h02;
  localparam  INIT_CAL4_READ            = 5'h03;
  localparam  INIT_CAL1_WRITE           = 5'h04;
  localparam  INIT_CAL2_WRITE           = 5'h05;
  localparam  INIT_CAL3_WRITE           = 5'h06;
  localparam  INIT_DUMMY_ACTIVE_WAIT    = 5'h07;
  localparam  INIT_PRECHARGE            = 5'h08;
  localparam  INIT_LOAD_MODE            = 5'h09;
  localparam  INIT_AUTO_REFRESH         = 5'h0A;
  localparam  INIT_IDLE                 = 5'h0B;
  localparam  INIT_CNT_200              = 5'h0C;
  localparam  INIT_CNT_200_WAIT         = 5'h0D;
  localparam  INIT_PRECHARGE_WAIT       = 5'h0E;
  localparam  INIT_MODE_REGISTER_WAIT   = 5'h0F;
  localparam  INIT_AUTO_REFRESH_WAIT    = 5'h10;
  localparam  INIT_DEEP_MEMORY_ST       = 5'h11;
  localparam  INIT_DUMMY_ACTIVE         = 5'h12;
  localparam  INIT_CAL1_WRITE_READ      = 5'h13;
  localparam  INIT_CAL1_READ_WAIT       = 5'h14;
  localparam  INIT_CAL2_WRITE_READ      = 5'h15;
  localparam  INIT_CAL2_READ_WAIT       = 5'h16;
  localparam  INIT_CAL3_WRITE_READ      = 5'h17;
  localparam  INIT_CAL3_READ_WAIT       = 5'h18;
  localparam  INIT_CAL4_READ_WAIT       = 5'h19;
  localparam  INIT_CALIB_REF            = 5'h1A;
  localparam  INIT_ZQCL                 = 5'h1B;
  localparam  INIT_WAIT_DLLK_ZQINIT     = 5'h1C;

  localparam  INIT_CNTR_INIT            = 4'h0;
  localparam  INIT_CNTR_PRECH_1         = 4'h1;
  localparam  INIT_CNTR_EMR2_INIT       = 4'h2;
  localparam  INIT_CNTR_EMR3_INIT       = 4'h3;
  localparam  INIT_CNTR_EMR_EN_DLL      = 4'h4;
  localparam  INIT_CNTR_MR_RST_DLL      = 4'h5;
  localparam  INIT_CNTR_CNT_200_WAIT    = 4'h6;
  localparam  INIT_CNTR_PRECH_2         = 4'h7;
  localparam  INIT_CNTR_AR_1            = 4'h8;
  localparam  INIT_CNTR_AR_2            = 4'h9;
  localparam  INIT_CNTR_MR_ACT_DLL      = 4'hA;
  localparam  INIT_CNTR_EMR_DEF_OCD     = 4'hB;
  localparam  INIT_CNTR_EMR_EXIT_OCD    = 4'hC;
  localparam  INIT_CNTR_DEEP_MEM        = 4'hD;
  localparam  INIT_CNTR_PRECH_3         = 4'hE;
  localparam  INIT_CNTR_DONE            = 4'hF;

  localparam   DDR1                     = 0;
  localparam   DDR2                     = 1;
  localparam   DDR3                     = 2;


  reg [1:0]             burst_addr_r;
  reg [1:0]             burst_cnt_r;
  wire [1:0]            burst_val;
  wire                  cal_read;
  wire                  cal_write;
  wire                  cal_write_read;
  reg                   cal1_started_r;
  reg                   cal2_started_r;
  reg                   cal4_started_r;
  reg [3:0]             calib_done_r;
  reg                   calib_ref_req_posedge;
  reg                   calib_ref_req_r;
  reg [15:0]            calib_start_shift0_r;
  reg [15:0]            calib_start_shift1_r;
  reg [15:0]            calib_start_shift2_r;
  reg [15:0]            calib_start_shift3_r;
  reg [1:0]             chip_cnt_r;
  reg [4:0]             cke_200us_cnt_r;
  reg                   cke_200us_cnt_en_r;
  reg [7:0]             cnt_200_cycle_r;
  reg                   cnt_200_cycle_done_r;
  reg [6:0]             cnt_cmd_r;
  reg                   cnt_cmd_ok_r;
  reg [3:0]             cnt_rd_r;
  reg                   cnt_rd_ok_r;
  reg                   ctrl_ref_flag_r;
  reg                   done_200us_r;
  reg [ROW_WIDTH-1:0]   ddr_addr_r;
  reg [ROW_WIDTH-1:0]   ddr_addr_r1;
  reg [BANK_WIDTH-1:0]  ddr_ba_r;
  reg [BANK_WIDTH-1:0]  ddr_ba_r1;
  reg                   ddr_cas_n_r;
  reg                   ddr_cas_n_r1;
  reg [CKE_WIDTH-1:0]   ddr_cke_r;
  reg [CS_NUM-1:0]      ddr_cs_n_r;
  reg [CS_NUM-1:0]      ddr_cs_n_r1;
  reg [CS_NUM-1:0]      ddr_cs_disable_r;
  reg                   ddr_ras_n_r;
  reg                   ddr_ras_n_r1;
  reg                   ddr_we_n_r;
  reg                   ddr_we_n_r1;
  wire [15:0]           ext_mode_reg;
  reg [3:0]             init_cnt_r;
  reg                   init_done_r;
  reg [4:0]             init_next_state;
  reg [4:0]             init_state_r;
  reg [4:0]             init_state_r1;
  reg [4:0]             init_state_r2;
  wire [15:0]           load_mode_reg;
  wire [15:0]           load_mode_reg0;
  wire [15:0]           load_mode_reg1;
  wire [15:0]           load_mode_reg2;
  wire [15:0]           load_mode_reg3;
  reg                   phy_init_done_r;
  reg                   phy_init_done_r1;
  reg                   phy_init_done_r2;
  reg                   phy_init_done_r3;
  reg                   refresh_req;
  wire [3:0]            start_cal;

  //***************************************************************************

  //*****************************************************************
  // DDR1 and DDR2 Load mode register
  // Mode Register (MR):
  //   [15:14] - unused          - 00
  //   [13]    - reserved        - 0
  //   [12]    - Power-down mode - 0 (normal)
  //   [11:9]  - write recovery  - same value as written to CAS LAT
  //   [8]     - DLL reset       - 0 or 1
  //   [7]     - Test Mode       - 0 (normal)
  //   [6:4]   - CAS latency     - CAS_LAT
  //   [3]     - Burst Type      - BURST_TYPE
  //   [2:0]   - Burst Length    - BURST_LEN
  //*****************************************************************

  generate
    if (DDR_TYPE == DDR2) begin: gen_load_mode_reg_ddr2
      assign load_mode_reg[2:0]   = (BURST_LEN == 8) ? 3'b011 :
                                    ((BURST_LEN == 4) ? 3'b010 : 3'b111);
      assign load_mode_reg[3]     = BURST_TYPE;
      assign load_mode_reg[6:4]   = (CAS_LAT == 3) ? 3'b011 :
                                    ((CAS_LAT == 4) ? 3'b100 :
                                     ((CAS_LAT == 5) ? 3'b101 : 3'b111));
      assign load_mode_reg[7]     = 1'b0;
      assign load_mode_reg[8]     = 1'b0;    // init value only (DLL not reset)
      assign load_mode_reg[11:9]  = load_mode_reg[6:4];
      assign load_mode_reg[15:12] = 4'b000;
    end else if (DDR_TYPE == DDR1)begin: gen_load_mode_reg_ddr1
      assign load_mode_reg[2:0]   = (BURST_LEN == 8) ? 3'b011 :
                                    ((BURST_LEN == 4) ? 3'b010 :
                                     ((BURST_LEN == 2) ? 3'b001 : 3'b111));
      assign load_mode_reg[3]     = BURST_TYPE;
      assign load_mode_reg[6:4]   = (CAS_LAT == 2) ? 3'b010 :
                                    ((CAS_LAT == 3) ? 3'b011 :
                                     ((CAS_LAT == 25) ? 3'b110 : 3'b111));
      assign load_mode_reg[12:7]  = 6'b000000; // init value only
      assign load_mode_reg[15:13]  = 3'b000;
    end
  endgenerate

  //*****************************************************************
  // DDR1 and DDR2 ext mode register
  // Extended Mode Register (MR):
  //   [15:14] - unused          - 00
  //   [13]    - reserved        - 0
  //   [12]    - output enable   - 0 (enabled)
  //   [11]    - RDQS enable     - 0 (disabled)
  //   [10]    - DQS# enable     - 0 (enabled)
  //   [9:7]   - OCD Program     - 111 or 000 (first 111, then 000 during init)
  //   [6]     - RTT[1]          - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50)
  //   [5:3]   - Additive CAS    - ADDITIVE_CAS
  //   [2]     - RTT[0]
  //   [1]     - Output drive    - REDUCE_DRV (= 0(full), = 1 (reduced)
  //   [0]     - DLL enable      - 0 (normal)
  //*****************************************************************

  generate
    if (DDR_TYPE == DDR2) begin: gen_ext_mode_reg_ddr2
      assign ext_mode_reg[0]     = 1'b0;
      assign ext_mode_reg[1]     = REDUCE_DRV;
      assign ext_mode_reg[2]     = ((ODT_TYPE == 1) || (ODT_TYPE == 3)) ?
                                   1'b1 : 1'b0;
      assign ext_mode_reg[5:3]   = (ADDITIVE_LAT == 0) ? 3'b000 :
                                   ((ADDITIVE_LAT == 1) ? 3'b001 :
                                    ((ADDITIVE_LAT == 2) ? 3'b010 :
                                     ((ADDITIVE_LAT == 3) ? 3'b011 :
                                      ((ADDITIVE_LAT == 4) ? 3'b100 :
                                      3'b111))));
      assign ext_mode_reg[6]     = ((ODT_TYPE == 2) || (ODT_TYPE == 3)) ?
                                   1'b1 : 1'b0;
      assign ext_mode_reg[9:7]   = 3'b000;
      assign ext_mode_reg[10]    = 1'b0;
      assign ext_mode_reg[15:10] = 6'b000000;
    end else if (DDR_TYPE == DDR1)begin: gen_ext_mode_reg_ddr1
      assign ext_mode_reg[0]     = 1'b0;
      assign ext_mode_reg[1]     = REDUCE_DRV;
      assign ext_mode_reg[12:2]  = 11'b00000000000;
      assign ext_mode_reg[15:13] = 3'b000;
    end
  endgenerate

  //*****************************************************************
  // DDR3 Load mode reg0
  // Mode Register (MR0):
  //   [15:13] - unused          - 000
  //   [12]    - Precharge Power-down DLL usage - 0 (DLL frozen, slow-exit),
  //             1 (DLL maintained)
  //   [11:9]  - write recovery for Auto Precharge (tWR/tCK = 6)
  //   [8]     - DLL reset       - 0 or 1
  //   [7]     - Test Mode       - 0 (normal)
  //   [6:4],[2]   - CAS latency     - CAS_LAT
  //   [3]     - Burst Type      - BURST_TYPE
  //   [1:0]   - Burst Length    - BURST_LEN
  //*****************************************************************

  generate
    if (DDR_TYPE == DDR3) begin: gen_load_mode_reg0_ddr3
      assign load_mode_reg0[1:0]   = (BURST_LEN == 8) ? 2'b00 :
                                     ((BURST_LEN == 4) ? 2'b10 : 2'b11);
      // Part of CAS latency. This bit is '0' for all CAS latencies
      assign load_mode_reg0[2]     = 1'b0;
      assign load_mode_reg0[3]     = BURST_TYPE;
      assign load_mode_reg0[6:4]   = (CAS_LAT == 5) ? 3'b001 :
                                     (CAS_LAT == 6) ? 3'b010 : 3'b111;
      assign load_mode_reg0[7]     = 1'b0;
      // init value only (DLL reset)
      assign load_mode_reg0[8]     = 1'b1;
      assign load_mode_reg0[11:9]  = 3'b010;
      // Precharge Power-Down DLL 'slow-exit'
      assign load_mode_reg0[12]    = 1'b0;
      assign load_mode_reg0[15:13] = 3'b000;
    end
  endgenerate

  //*****************************************************************
  // DDR3 Load mode reg1
  // Mode Register (MR1):
  //   [15:13] - unused          - 00
  //   [12]    - output enable   - 0 (enabled for DQ, DQS, DQS#)
  //   [11]    - TDQS enable     - 0 (TDQS disabled and DM enabled)
  //   [10]    - reserved   - 0 (must be '0')
  //   [9]     - RTT[2]     - 0
  //   [8]     - reserved   - 0 (must be '0')
  //   [7]     - write leveling - 0 (disabled), 1 (enabled)
  //   [6]     - RTT[1]          - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50)
  //   [5]     - Output driver impedance[1] - 0 (RZQ/6 and RZQ/7)
  //   [4:3]   - Additive CAS    - ADDITIVE_CAS
  //   [2]     - RTT[0]
  //   [1]     - Output driver impedance[0] - 0(RZQ/6), or 1 (RZQ/7)
  //   [0]     - DLL enable      - 0 (normal)
  //*****************************************************************

  generate
    if (DDR_TYPE == DDR3) begin: gen_ext_mode_reg1_ddr3
      // DLL enabled during Imitialization
      assign load_mode_reg1[0]     = 1'b0;
      // RZQ/6
      assign load_mode_reg1[1]     = REDUCE_DRV;
      assign load_mode_reg1[2]     = ((ODT_TYPE == 1) || (ODT_TYPE == 3)) ?
                                     1'b1 : 1'b0;
      assign load_mode_reg1[4:3]   = (ADDITIVE_LAT == 0) ? 2'b00 :
                                     ((ADDITIVE_LAT == 1) ? 2'b01 :
                                      ((ADDITIVE_LAT == 2) ? 2'b10 :
                                       3'b111));