phy_write.v

DDR2源代码 DDR2源代码 DDR2源代码

//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This text/file contains proprietary, confidential
// information of Xilinx, Inc., is distributed under license
// from Xilinx, Inc., and may be used, copied and/or
// disclosed only pursuant to the terms of a valid license
// agreement with Xilinx, Inc. Xilinx hereby grants you a
// license to use this text/file solely for design, simulation,
// implementation and creation of design files limited
// to Xilinx devices or technologies. Use with non-Xilinx
// devices or technologies is expressly prohibited and
// immediately terminates your license unless covered by
// a separate agreement.
//
// Xilinx is providing this design, code, or information
// "as-is" solely for use in developing programs and
// solutions for Xilinx devices, with no obligation on the
// part of Xilinx to provide support. By providing this design,
// code, or information as one possible implementation of
// this feature, application or standard, Xilinx is making no
// representation that this implementation is free from any
// claims of infringement. You are responsible for
// obtaining any rights you may require for your implementation.
// Xilinx expressly disclaims any warranty whatsoever with
// respect to the adequacy of the implementation, including
// but not limited to any warranties or representations that this
// implementation is free from claims of infringement, implied
// warranties of merchantability or fitness for a particular
// purpose.
//
// Xilinx products are not intended for use in life support
// appliances, devices, or systems. Use in such applications is
// expressly prohibited.
//
// Any modifications that are made to the Source Code are
// done at the user抯 sole risk and will be unsupported.
//
// Copyright (c) 2006-2007 Xilinx, Inc. All rights reserved.
//
// This copyright and support notice must be retained as part
// of this text at all times.
//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 2.1
//  \   \         Application: MIG
//  /   /         Filename: phy_write.v
// /___/   /\     Date Last Modified: $Date: 2007/12/15 04:53:04 $
// \   \  /  \    Date Created: Thu Aug 24 2006
//  \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
//Reference:
//   Handles delaying various write control signals appropriately depending
//   on CAS latency, additive latency, etc. Also splits the data and mask in
//   rise and fall buses.
//Revision History:
//*****************************************************************************

`timescale 1ns/1ps

module phy_write #
  (
   // Following parameters are for 72-bit RDIMM design (for ML561 Reference
   // board design). Actual values may be different. Actual parameters values
   // are passed from design top module ddr2_sdram module. Please refer to
   // the ddr2_sdram module for actual values.
   parameter DQ_WIDTH      = 72,
   parameter ADDITIVE_LAT  = 0,
   parameter CAS_LAT       = 5,
   parameter ECC_ENABLE    = 0,
   parameter ODT_TYPE      = 1,
   parameter REG_ENABLE    = 1,
   parameter DDR_TYPE      = 1
   )
  (
   input                       clk0,
   input                       clk90,
   input                       rst90,
   input [(2*DQ_WIDTH)-1:0]    wdf_data,
   input [(2*DQ_WIDTH/8)-1:0]  wdf_mask_data,
   input                       ctrl_wren,
   input                       phy_init_wren,
   input                       phy_init_data_sel,
   output reg                  dm_ce,
   output reg [1:0]            dq_oe_n,
   output reg                  dqs_oe_n ,
   output reg                  dqs_rst_n ,
   output                      wdf_rden,
   output reg                  odt ,
   output [DQ_WIDTH-1:0]       wr_data_rise,
   output [DQ_WIDTH-1:0]       wr_data_fall,
   output [(DQ_WIDTH/8)-1:0]   mask_data_rise,
   output [(DQ_WIDTH/8)-1:0]   mask_data_fall
   );

  localparam   MASK_WIDTH               = DQ_WIDTH/8;
  localparam   DDR1                     = 0;
  localparam   DDR2                     = 1;
  localparam   DDR3                     = 2;

  // (MIN,MAX) value of WR_LATENCY for DDR1:
  //   REG_ENABLE   = (0,1)
  //   ECC_ENABLE   = (0,1)
  //   Write latency = 1
  //   Total: (1,3)
  // (MIN,MAX) value of WR_LATENCY for DDR2:
  //   REG_ENABLE   = (0,1)
  //   ECC_ENABLE   = (0,1)
  //   Write latency = ADDITIVE_CAS + CAS_LAT - 1 = (0,4) + (3,5) - 1 = (2,8)
  //     ADDITIVE_LAT = (0,4) (JEDEC79-2B)
  //     CAS_LAT      = (3,5) (JEDEC79-2B)
  //   Total: (2,10)
  localparam WR_LATENCY = (DDR_TYPE == DDR3) ?
             (ADDITIVE_LAT + (CAS_LAT) + REG_ENABLE ) :
             (DDR_TYPE == DDR2) ?
             (ADDITIVE_LAT + (CAS_LAT-1) + REG_ENABLE ) :
             (1 + REG_ENABLE );

  // NOTE that ODT timing does not need to be delayed for registered
  // DIMM case, since like other control/address signals, it gets
  // delayed by one clock cycle at the DIMM
  localparam ODT_WR_LATENCY = WR_LATENCY - REG_ENABLE;

  wire                     dm_ce_0;
  reg                      dm_ce_r;
  wire [1:0]               dq_oe_0;
  reg [1:0]                dq_oe_n_90_r1;
  reg [1:0]                dq_oe_270;
  wire                     dqs_oe_0;
  reg                      dqs_oe_270;
  reg                      dqs_oe_n_180_r1;
  wire                     dqs_rst_0;
  reg                      dqs_rst_n_180_r1;
  reg                      dqs_rst_270;
  reg                      ecc_dm_error_r;
  reg                      ecc_dm_error_r1;
  reg [(DQ_WIDTH-1):0]     init_data_f;
  reg [(DQ_WIDTH-1):0]     init_data_r;
  reg [3:0]                init_wdf_cnt_r;
  wire                     odt_0;
  reg                      rst90_r /* synthesis syn_maxfan = 10 */;
  reg [10:0]               wr_stages ;
  reg [(2*DQ_WIDTH)-1:0]   wdf_data_r;
  reg [(2*DQ_WIDTH/8)-1:0] wdf_mask_r;
  wire [(2*DQ_WIDTH/8)-1:0] wdf_ecc_mask;

  reg [(2*DQ_WIDTH/8)-1:0] wdf_mask_r1;
  wire                     wdf_rden_0;
  reg                      calib_rden_90_r;
  reg                      wdf_rden_90_r;
  reg                      wdf_rden_90_r1;
  reg                      wdf_rden_270;

  always @(posedge clk90)
      rst90_r <= rst90;

  //***************************************************************************
  // Analysis of additional pipeline delays:
  //   1. dq_oe (DQ 3-state): 1 CLK90 cyc in IOB 3-state FF
  //   2. dqs_oe (DQS 3-state): 1 CLK180 cyc in IOB 3-state FF
  //   3. dqs_rst (DQS output value reset): 1 CLK180 cyc in FF + 1 CLK180 cyc
  //      in IOB DDR
  //   4. odt (ODT control): 1 CLK0 cyc in IOB FF
  //   5. write data (output two cyc after wdf_rden - output of RAMB_FIFO w/
  //      output register enabled): 2 CLK90 cyc in OSERDES
  //***************************************************************************

  // DQS 3-state must be asserted one extra clock cycle due b/c of write
  // pre- and post-amble (extra half clock cycle for each)
  assign dqs_oe_0 = wr_stages[WR_LATENCY-1] | wr_stages[WR_LATENCY-2];

  // same goes for ODT, need to handle both pre- and post-amble (generate
  // ODT only for DDR2)
  // ODT generation for DDR2 based on write latency. The MIN write
  // latency is 2. Based on the write latency ODT is asserted.
  generate
    if ((DDR_TYPE != DDR1) && (ODT_TYPE > 0))begin: gen_odt_ddr2
       if(ODT_WR_LATENCY > 2)
         assign odt_0 =
                   wr_stages[ODT_WR_LATENCY-1] |
                   wr_stages[ODT_WR_LATENCY-2] |
                   wr_stages[ODT_WR_LATENCY-3] ;
       else
         assign odt_0 =
                  wr_stages[ODT_WR_LATENCY] |
                  wr_stages[ODT_WR_LATENCY-1] |
                  wr_stages[ODT_WR_LATENCY-2] ;
    end else
      assign odt_0 = 1'b0;
   endgenerate

  assign dq_oe_0[0]   = wr_stages[WR_LATENCY-1] | wr_stages[WR_LATENCY];
  assign dq_oe_0[1]   = wr_stages[WR_LATENCY-1] | wr_stages[WR_LATENCY-2];
  assign dqs_rst_0    = ~wr_stages[WR_LATENCY-2];
  assign dm_ce_0      = wr_stages[WR_LATENCY] | wr_stages[WR_LATENCY-1]
                        | wr_stages[WR_LATENCY-2];

  // write data fifo, read flag assertion
  generate
    if (DDR_TYPE != DDR1) begin: gen_wdf_ddr2
      if (WR_LATENCY > 2)
        assign wdf_rden_0 = wr_stages[WR_LATENCY-3];
      else
        assign wdf_rden_0 = wr_stages[WR_LATENCY-2];
    end else begin: gen_wdf_ddr1
      assign wdf_rden_0 = wr_stages[WR_LATENCY-2];
    end
  endgenerate

  // first stage isn't registered
  always @(*)
    wr_stages[0] = (phy_init_data_sel) ? ctrl_wren : phy_init_wren;

  always @(posedge clk0) begin
    wr_stages[1] <= wr_stages[0];
    wr_stages[2] <= wr_stages[1];