phy_calib.v

DDR2源代码 DDR2源代码 DDR2源代码

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//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 2.1
//  \   \         Application: MIG
//  /   /         Filename: phy_calib.v
// /___/   /\     Date Last Modified: $Date: 2007/12/15 04:53:04 $
// \   \  /  \    Date Created: Thu Aug 10 2006
//  \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
//   This module handles calibration after memory initialization.
//Reference:
//Revision History:
//*****************************************************************************

`timescale 1ns/1ps

module phy_calib #
  (
   // Following parameters are for 72-bit RDIMM design (for ML561 Reference 
   // board design). Actual values may be different. Actual parameters values 
   // are passed from design top module ddr2_sdram module. Please refer to
   // the ddr2_sdram module for actual values.
   parameter DQ_WIDTH      = 72,
   parameter DQ_BITS       = 7,
   parameter DQ_PER_DQS    = 8,
   parameter DQS_BITS      = 4,
   parameter DQS_WIDTH     = 9,
   parameter ADDITIVE_LAT  = 0,
   parameter CAS_LAT       = 5,
   parameter REG_ENABLE    = 1,
   parameter CLK_PERIOD    = 3000,
   parameter SIM_ONLY      = 0,
   parameter DEBUG_EN      = 0
   )
  (
   input                                   clk,
   input                                   clkdiv,
   input                                   rstdiv,
   input [3:0]                             calib_start,
   input                                   ctrl_rden,
   input                                   phy_init_rden,
   input [DQ_WIDTH-1:0]                    rd_data_rise,
   input [DQ_WIDTH-1:0]                    rd_data_fall,
   input                                   calib_ref_done,
   output reg [3:0]                        calib_done,
   output reg                              calib_ref_req,
   output [DQS_WIDTH-1:0]                  calib_rden,
   output reg [DQS_WIDTH-1:0]              calib_rden_sel,
   output reg                              dlyrst_dq,
   output reg [DQ_WIDTH-1:0]               dlyce_dq,
   output reg [DQ_WIDTH-1:0]               dlyinc_dq,
   output reg                              dlyrst_dqs,
   output reg [DQS_WIDTH-1:0]              dlyce_dqs,
   output reg [DQS_WIDTH-1:0]              dlyinc_dqs,
   output reg [DQS_WIDTH-1:0]              dlyrst_gate,
   output reg [DQS_WIDTH-1:0]              dlyce_gate,
   output reg [DQS_WIDTH-1:0]              dlyinc_gate,
   output [DQS_WIDTH-1:0]                  en_dqs,
   output [DQS_WIDTH-1:0]                  rd_data_sel,
   // Debug signals (optional use)
   input                                   dbg_idel_up_all,
   input                                   dbg_idel_down_all,
   input                                   dbg_idel_up_dq,
   input                                   dbg_idel_down_dq,
   input                                   dbg_idel_up_dqs,
   input                                   dbg_idel_down_dqs,
   input                                   dbg_idel_up_gate,
   input                                   dbg_idel_down_gate,
   input [DQ_BITS-1:0]                     dbg_sel_idel_dq,
   input                                   dbg_sel_all_idel_dq,
   input [DQS_BITS:0]                      dbg_sel_idel_dqs,
   input                                   dbg_sel_all_idel_dqs,
   input [DQS_BITS:0]                      dbg_sel_idel_gate,
   input                                   dbg_sel_all_idel_gate,
   output [3:0]                            dbg_calib_done,
   output [3:0]                            dbg_calib_err,
   output [(6*DQ_WIDTH)-1:0]               dbg_calib_dq_tap_cnt,
   output [(6*DQS_WIDTH)-1:0]              dbg_calib_dqs_tap_cnt,
   output [(6*DQS_WIDTH)-1:0]              dbg_calib_gate_tap_cnt,
   output [DQS_WIDTH-1:0]                  dbg_calib_rd_data_sel,
   output [(5*DQS_WIDTH)-1:0]              dbg_calib_rden_dly,
   output [(5*DQS_WIDTH)-1:0]              dbg_calib_gate_dly
   );

  // minimum time (in IDELAY taps) for which capture data must be stable for
  // algorithm to consider
  localparam MIN_WIN_SIZE = 5;
  // IDEL_SET_VAL = (# of cycles - 1) to wait after changing IDELAY value
  // we only have to wait enough for input with new IDELAY value to
  // propagate through pipeline stages.
  localparam IDEL_SET_VAL = 3'b111;
  // # of clock cycles to delay read enable to determine if read data pattern
  // is correct for stage 3/4 (RDEN, DQS gate) calibration
  localparam CALIB_RDEN_PIPE_LEN = 31;
  // translate CAS latency into number of clock cycles for read valid delay
  // determination. Really only needed for CL = 2.5 (set to 2)
  localparam CAS_LAT_RDEN = (CAS_LAT == 25) ? 2 : CAS_LAT;
  // an SRL32 is used to delay CTRL_RDEN to generate read valid signal. This
  // is min possible value delay through SRL32 can be
  localparam RDEN_BASE_DELAY = CAS_LAT_RDEN + ADDITIVE_LAT + REG_ENABLE;
  // an SRL32 is used to delay the CTRL_RDEN from the read postamble DQS
  // gate. This is min possible value the SRL32 delay can be:
  //  - Delay from end of deassertion of CTRL_RDEN to last falling edge of
  //    read burst = 3.5 (CTRL_RDEN -> CAS delay) + 3 (min CAS latency) = 6.5
  //  - Minimum time for DQS gate circuit to be generated:
  //      * 1 cyc to register CTRL_RDEN from controller
  //      * 1 cyc after RDEN_CTRL falling edge
  //      * 1 cyc min through SRL32
  //      * 1 cyc through SRL32 output flop
  //      * 0 (<1) cyc of synchronization to DQS domain via IDELAY
  //      * 1 cyc of delay through IDDR to generate CE to DQ IDDR's
  //    Total = 5 cyc < 6.5 cycles
  //    The total should be less than 5.5 cycles to account prop delays
  //    adding one cycle to the synchronization time via the IDELAY.
  //    NOTE: Value differs because of optional pipeline register added
  //      for case of RDEN_BASE_DELAY > 3 to improve timing
  localparam GATE_BASE_DELAY = RDEN_BASE_DELAY - 3;
  localparam GATE_BASE_INIT = (GATE_BASE_DELAY <= 1) ? 0 : GATE_BASE_DELAY;
  // used for RDEN calibration: difference between shift value used during
  // calibration, and shift value for actual RDEN SRL. Only applies when
  // RDEN edge is immediately captured by CLKDIV0. If not (depends on phase
  // of CLK0 and CLKDIV0 when RDEN is asserted), then add 1 to this value.
  localparam CAL3_RDEN_SRL_DLY_DELTA = 6;
  // fix minimum value of DQS to be 1 to handle the case where's there's only
  // one DQS group. We could also enforce that user always inputs minimum
  // value of 1 for DQS_BITS (even when DQS_WIDTH=1). Leave this as safeguard
  // Assume we don't have to do this for DQ, DQ_WIDTH always > 1
  localparam DQS_BITS_FIX = (DQS_BITS == 0) ? 1 : DQS_BITS;
  // how many taps to "pre-delay" DQ before stg 1 calibration - not needed for
  // current calibration, but leave for debug
  localparam DQ_IDEL_INIT = 6'b000000;
  // # IDELAY taps per bit time (i.e. half cycle). Limit to 63.
  localparam integer BIT_TIME_TAPS = (CLK_PERIOD/150 < 64) ?
             CLK_PERIOD/150 : 63;

  // used in various places during stage 4 cal: (1) determines maximum taps
  // to increment when finding right edge, (2) amount to decrement after
  // finding left edge, (3) amount to increment after finding right edge
  localparam CAL4_IDEL_BIT_VAL = (BIT_TIME_TAPS >= 6'b100000) ?
             6'b100000 : BIT_TIME_TAPS;

  localparam CAL1_IDLE                   = 4'h0;
  localparam CAL1_INIT                   = 4'h1;
  localparam CAL1_INC_IDEL               = 4'h2;
  localparam CAL1_FIND_FIRST_EDGE        = 4'h3;
  localparam CAL1_FIRST_EDGE_IDEL_WAIT   = 4'h4;
  localparam CAL1_FOUND_FIRST_EDGE_WAIT  = 4'h5;
  localparam CAL1_FIND_SECOND_EDGE       = 4'h6;
  localparam CAL1_SECOND_EDGE_IDEL_WAIT  = 4'h7;
  localparam CAL1_CALC_IDEL              = 4'h8;
  localparam CAL1_DEC_IDEL               = 4'h9;
  localparam CAL1_DONE                   = 4'hA;

  localparam CAL2_IDLE                    = 4'h0;
  localparam CAL2_INIT                    = 4'h1;
  localparam CAL2_INIT_IDEL_WAIT          = 4'h2;
  localparam CAL2_FIND_EDGE_POS           = 4'h3;
  localparam CAL2_FIND_EDGE_IDEL_WAIT_POS = 4'h4;
  localparam CAL2_FIND_EDGE_NEG           = 4'h5;
  localparam CAL2_FIND_EDGE_IDEL_WAIT_NEG = 4'h6;
  localparam CAL2_DEC_IDEL                = 4'h7;
  localparam CAL2_DONE                    = 4'h8;

  localparam CAL3_IDLE                    = 3'h0;
  localparam CAL3_INIT                    = 3'h1;
  localparam CAL3_DETECT                  = 3'h2;
  localparam CAL3_RDEN_PIPE_CLR_WAIT      = 3'h3;
  localparam CAL3_DONE                    = 3'h4;

  localparam CAL4_IDLE                    = 3'h0;
  localparam CAL4_INIT                    = 3'h1;
  localparam CAL4_FIND_WINDOW             = 3'h2;
  localparam CAL4_FIND_EDGE               = 3'h3;
  localparam CAL4_IDEL_WAIT               = 3'h4;
  localparam CAL4_RDEN_PIPE_CLR_WAIT      = 3'h5;
  localparam CAL4_ADJ_IDEL                = 3'h6;
  localparam CAL4_DONE                    = 3'h7;

  integer                        i, j;

  reg [5:0]                      cal1_bit_time_tap_cnt;
  reg [1:0]                      cal1_data_chk_last;
  reg                            cal1_data_chk_last_valid;
  reg [1:0]                      cal1_data_chk_r;
  reg                            cal1_dlyce_dq;
  reg                            cal1_dlyinc_dq;
  reg                            cal1_dqs_dq_init_phase;
  reg                            cal1_detect_edge;
  reg                            cal1_detect_stable;
  reg                            cal1_found_second_edge;
  reg                            cal1_found_rising;
  reg                            cal1_found_window;
  reg                            cal1_first_edge_done;
  reg [5:0]                      cal1_first_edge_tap_cnt;
  reg [6:0]                      cal1_idel_dec_cnt;
  reg [5:0]                      cal1_idel_inc_cnt;
  reg [5:0]                      cal1_idel_max_tap;
  reg                            cal1_idel_max_tap_we;
  reg [5:0]                      cal1_idel_tap_cnt;
  reg                            cal1_idel_tap_limit_hit;
  reg [6:0]                      cal1_low_freq_idel_dec;
  reg                            cal1_ref_req;
  wire                           cal1_refresh;
  reg [3:0]                      cal1_state;
  reg [3:0]                      cal1_window_cnt;
  reg                            cal2_curr_sel;
  wire                           cal2_detect_edge;
  reg                            cal2_dlyce_dqs;
  reg                            cal2_dlyinc_dqs;
  reg [5:0]                      cal2_idel_dec_cnt;
  reg [5:0]                      cal2_idel_tap_cnt;
  reg [5:0]                      cal2_idel_tap_limit;
  reg                            cal2_idel_tap_limit_hit;
  reg                            cal2_rd_data_fall_last_neg;
  reg                            cal2_rd_data_fall_last_pos;
  reg                            cal2_rd_data_last_valid_neg;
  reg                            cal2_rd_data_last_valid_pos;
  reg                            cal2_rd_data_rise_last_neg;
  reg                            cal2_rd_data_rise_last_pos;
  reg [DQS_WIDTH-1:0]            cal2_rd_data_sel;
  wire                           cal2_rd_data_sel_edge;
  reg [DQS_WIDTH-1:0]            cal2_rd_data_sel_r;
  reg                            cal2_ref_req;
  reg [3:0]                      cal2_state;
  reg                            cal3_data_match;
  reg                            cal3_data_match_stgd;
  wire                           cal3_data_valid;
  wire                           cal3_match_found;
  wire [4:0]                     cal3_rden_dly;
  reg [4:0]                      cal3_rden_srl_a;
  reg [2:0]                      cal3_state;
  wire                           cal4_data_good;
  reg                            cal4_data_match;
  reg                            cal4_data_match_stgd;
  wire                           cal4_data_valid;