phy_top.v

DDR2源代码 DDR2源代码 DDR2源代码

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//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 2.1
//  \   \         Application: MIG
//  /   /         Filename: phy_top.v
// /___/   /\     Date Last Modified: $Date: 2007/11/28 13:20:56 $
// \   \  /  \    Date Created: Wed Aug 16 2006
//  \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
//   Top-level for memory physical layer (PHY) interface
//Reference:
//Revision History:
//*****************************************************************************

`timescale 1ns/1ps

module phy_top #
  (
   // Following parameters are for 72-bit RDIMM design (for ML561 Reference 
   // board design). Actual values may be different. Actual parameters values 
   // are passed from design top module ddr2_sdram module. Please refer to
   // the ddr2_sdram module for actual values.
   parameter BANK_WIDTH     = 2,
   parameter CLK_WIDTH      = 1,
   parameter CKE_WIDTH      = 1,
   parameter COL_WIDTH      = 10,
   parameter CS_NUM         = 1,
   parameter CS_WIDTH       = 1,
   parameter DM_WIDTH       = 9,
   parameter DQ_WIDTH       = 72,
   parameter DQ_BITS        = 7,
   parameter DQ_PER_DQS     = 8,
   parameter DQS_WIDTH      = 9,
   parameter DQS_BITS       = 4,
   parameter ODT_WIDTH      = 1,
   parameter ROW_WIDTH      = 14,
   parameter ADDITIVE_LAT   = 0,
   parameter TWO_T_TIME_EN  = 0,
   parameter BURST_LEN      = 4,
   parameter BURST_TYPE     = 0,
   parameter CAS_LAT        = 5,
   parameter ECC_ENABLE     = 0,
   parameter ODT_TYPE       = 1,
   parameter DDR_TYPE       = 1,
   parameter REDUCE_DRV     = 0,
   parameter REG_ENABLE     = 1,
   parameter CLK_PERIOD     = 3000,
   parameter SIM_ONLY       = 0,
   parameter DEBUG_EN       = 0,
   parameter DQS_IO_COL     = 0,
   parameter DQ_IO_MS       = 0
   )
  (
   input                                  clk0,
   input                                  clk90,
   input                                  clkdiv0,
   input                                  rst0,
   input                                  rst90,
   input                                  rstdiv0,
   input                                  ctrl_wren,
   input [ROW_WIDTH-1:0]                  ctrl_addr,
   input [BANK_WIDTH-1:0]                 ctrl_ba,
   input                                  ctrl_ras_n,
   input                                  ctrl_cas_n,
   input                                  ctrl_we_n,
   input [CS_NUM-1:0]                     ctrl_cs_n,
   input                                  ctrl_rden,
   input                                  ctrl_ref_flag,
   input [(2*DQ_WIDTH)-1:0]               wdf_data,
   input [(2*DQ_WIDTH/8)-1:0]             wdf_mask_data,
   output                                 wdf_rden,
   output                                 phy_init_done,
   output [DQS_WIDTH-1:0]                 phy_calib_rden,
   output [DQS_WIDTH-1:0]                 phy_calib_rden_sel,
   output [DQ_WIDTH-1:0]                  rd_data_rise,
   output [DQ_WIDTH-1:0]                  rd_data_fall,
   output [CLK_WIDTH-1:0]                 ddr_ck,
   output [CLK_WIDTH-1:0]                 ddr_ck_n,
   output [ROW_WIDTH-1:0]                 ddr_addr,
   output [BANK_WIDTH-1:0]                ddr_ba,
   output                                 ddr_ras_n,
   output                                 ddr_cas_n,
   output                                 ddr_we_n,
   output [CS_WIDTH-1:0]                  ddr_cs_n,
   output [CKE_WIDTH-1:0]                 ddr_cke,
   output [ODT_WIDTH-1:0]                 ddr_odt,
   output [DM_WIDTH-1:0]                  ddr_dm,
   inout [DQS_WIDTH-1:0]                  ddr_dqs,
   inout [DQS_WIDTH-1:0]                  ddr_dqs_n,
   inout [DQ_WIDTH-1:0]                   ddr_dq,
   // Debug signals (optional use)
   input                                  dbg_idel_up_all,
   input                                  dbg_idel_down_all,
   input                                  dbg_idel_up_dq,
   input                                  dbg_idel_down_dq,
   input                                  dbg_idel_up_dqs,
   input                                  dbg_idel_down_dqs,
   input                                  dbg_idel_up_gate,
   input                                  dbg_idel_down_gate,
   input [DQ_BITS-1:0]                    dbg_sel_idel_dq,
   input                                  dbg_sel_all_idel_dq,
   input [DQS_BITS:0]                     dbg_sel_idel_dqs,
   input                                  dbg_sel_all_idel_dqs,
   input [DQS_BITS:0]                     dbg_sel_idel_gate,
   input                                  dbg_sel_all_idel_gate,
   output [3:0]                           dbg_calib_done,
   output [3:0]                           dbg_calib_err,
   output [(6*DQ_WIDTH)-1:0]              dbg_calib_dq_tap_cnt,
   output [(6*DQS_WIDTH)-1:0]             dbg_calib_dqs_tap_cnt,
   output [(6*DQS_WIDTH)-1:0]             dbg_calib_gate_tap_cnt,
   output [DQS_WIDTH-1:0]                 dbg_calib_rd_data_sel,
   output [(5*DQS_WIDTH)-1:0]             dbg_calib_rden_dly,
   output [(5*DQS_WIDTH)-1:0]             dbg_calib_gate_dly
   );

  wire [3:0]               calib_done;
  wire                     calib_ref_done;
  wire                     calib_ref_req;
  wire [3:0]               calib_start;
  wire                     dm_ce;
  wire [1:0]               dq_oe_n;
  wire                     dqs_oe_n;
  wire                     dqs_rst_n;
  wire [(DQ_WIDTH/8)-1:0]  mask_data_fall;
  wire [(DQ_WIDTH/8)-1:0]  mask_data_rise;
  wire                     odt;
  wire [ROW_WIDTH-1:0]     phy_init_addr;
  wire [BANK_WIDTH-1:0]    phy_init_ba;
  wire                     phy_init_cas_n;
  wire [CKE_WIDTH-1:0]     phy_init_cke;
  wire [CS_NUM-1:0]        phy_init_cs_n;
  wire                     phy_init_data_sel;
  wire                     phy_init_ras_n;
  wire                     phy_init_rden;
  wire                     phy_init_we_n;
  wire                     phy_init_wren;
  wire [DQ_WIDTH-1:0]      wr_data_fall;
  wire [DQ_WIDTH-1:0]      wr_data_rise;

  // synthesis attribute X_CORE_INFO of phy_top is "mig_v2_1_ddr2_v5, Coregen 10.1i_ip0";

  // synthesis attribute CORE_GENERATION_INFO of ddr2_sdram is "ddr2_v5,mig_v2_1,{component_name=ddr2_v5, bank_width=2, cke_width=1, clk_width=1, col_width=9, cs_num=1, cs_width=1, dm_width=2, dq_width=16, dq_per_dqs=8, dqs_width=2, odt_width=1, row_width=13, additive_lat=0, burst_len=4, burst_type=0, cas_lat=5, ecc_enable=0, multi_bank_en=1, two_t_time_en=0, odt_type=1, reduce_drv=0, reg_enable=0, trefi_ns=7800, tras=40000, trcd=15000, trfc=75000, trp=15000, trtp=7500, twr=15000, twtr=7500, clk_period=3333, rst_act_low=1}";

  //***************************************************************************

  phy_write #
    (
     .DQ_WIDTH     (DQ_WIDTH),