glbl.v

DDR2源代码 DDR2源代码 DDR2源代码

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//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : 2.1
//  \   \        Application        : MIG
//  /   /        Filename           : glbl.v
// /___/   /\    Date Last Modified : $Date: 2008/01/09 15:43:36 $
// \   \  /  \   Date Created       : Wed Aug 16 2006
//  \___\/\___\
//
// Device      : Virtex-5
// Design Name : DDR2
// Purpose     : Used for intializing the simulation environment.
// Reference:
// Revision History:
//*****************************************************************************

`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

    wire GSR;
    wire GTS;
    wire PRLD;

    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

    assign (weak1, weak0) GSR = GSR_int;
    assign (weak1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
        GSR_int = 1'b1;
        PRLD_int = 1'b1;
        #(ROC_WIDTH)
        GSR_int = 1'b0;
        PRLD_int = 1'b0;
    end

    initial begin
        GTS_int = 1'b1;
        #(TOC_WIDTH)
        GTS_int = 1'b0;
    end

endmodule