📄 ddr2_sdram.v
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// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 2.1
// \ \ Application: MIG
// / / Filename: ddr2_sdram.v
// /___/ /\ Date Last Modified: $Date: 2007/12/19 15:42:27 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// Top-level module. This module serves both as an example, // and allows the user to synthesize a self-contained design, // which they can use to test their hardware.// In addition to the memory controller, the module instantiates:// 1. Clock generation/distribution, reset logic// 2. IDELAY control block// 3. Synthesizable testbench - used to model user's backend logic
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_sdram #
(
parameter BANK_WIDTH = 2, // # of memory bank addr bits
parameter CKE_WIDTH = 1, // # of memory clock enable outputs
parameter CLK_WIDTH = 1, // # of clock outputs
parameter COL_WIDTH = 9, // # of memory column bits
parameter CS_NUM = 1, // # of separate memory chip selects
parameter CS_WIDTH = 1, // # of total memory chip selects
parameter CS_BITS = 0, // set to log2(CS_NUM) (rounded up)
parameter DM_WIDTH = 2, // # of data mask bits
parameter DQ_WIDTH = 16, // # of data width
parameter DQ_PER_DQS = 8, // # of DQ data bits per strobe
parameter DQS_WIDTH = 2, // # of DQS strobes
parameter DQ_BITS = 4, // set to log2(DQS_WIDTH*DQ_PER_DQS)
parameter DQS_BITS = 1, // set to log2(DQS_WIDTH)
parameter ODT_WIDTH = 1, // # of memory on-die term enables
parameter ROW_WIDTH = 13, // # of memory row and # of addr bits
parameter ADDITIVE_LAT = 0, // additive write latency
parameter BURST_LEN = 4, // burst length (in double words)
parameter BURST_TYPE = 0, // burst type (=0 seq; =1 interleaved)
parameter CAS_LAT = 5, // CAS latency
parameter ECC_ENABLE = 0, // enable ECC (=1 enable)
parameter APPDATA_WIDTH = 32, // # of usr read/write data bus bits
parameter MULTI_BANK_EN = 1, // Keeps multiple banks open. (= 1 enable)
parameter TWO_T_TIME_EN = 0, // 2t timing for unbuffered dimms
parameter ODT_TYPE = 1, // ODT (=0(none),=1(75),=2(150),=3(50))
parameter REDUCE_DRV = 0, // reduced strength mem I/O (=1 yes)
parameter REG_ENABLE = 0, // registered addr/ctrl (=1 yes)
parameter TREFI_NS = 7800, // auto refresh interval (ns)
parameter TRAS = 40000, // active->precharge delay
parameter TRCD = 15000, // active->read/write delay
parameter TRFC = 75000, // refresh->refresh, refresh->active delay
parameter TRP = 15000, // precharge->command delay
parameter TRTP = 7500, // read->precharge delay
parameter TWR = 15000, // used to determine write->precharge
parameter TWTR = 7500, // write->read delay
parameter SIM_ONLY = 0, // = 1 to skip SDRAM power up delay
parameter DEBUG_EN = 0, // Enable debug signals/controls. When this parameter is changed from 0 to 1,
// make sure to uncomment the coregen commands in ise_flow.bat or create_ise.bat files in par folder.
parameter DQS_IO_COL = 4'b0000, // I/O column location of DQS groups (=0, left; =1 center, =2 right)
parameter DQ_IO_MS = 16'b10100101_10100101, // Master/Slave location of DQ I/O (=0 slave)
parameter CLK_PERIOD = 3333, // Core/Memory clock period (in ps)
parameter RST_ACT_LOW = 1, // =1 for active low reset, =0 for active high
parameter DLL_FREQ_MODE = "HIGH" // DCM Frequency range
)
(
inout [DQ_WIDTH-1:0] ddr2_dq,
output [ROW_WIDTH-1:0] ddr2_a,
output [BANK_WIDTH-1:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output [CS_WIDTH-1:0] ddr2_cs_n,
output [ODT_WIDTH-1:0] ddr2_odt,
output [CKE_WIDTH-1:0] ddr2_cke,
output [DM_WIDTH-1:0] ddr2_dm,
input sys_clk_p,
input sys_clk_n,
input clk200_p,
input clk200_n,
input sys_rst_n,
output phy_init_done,
output error,
inout [DQS_WIDTH-1:0] ddr2_dqs,
inout [DQS_WIDTH-1:0] ddr2_dqs_n,
output [CLK_WIDTH-1:0] ddr2_ck,
output [CLK_WIDTH-1:0] ddr2_ck_n
);
wire error_cmp;
wire rst0;
wire rst90;
wire rst200;
wire rstdiv0;
wire clk0;
wire clk90;
wire clk200;
wire clkdiv0;
wire idelay_ctrl_rdy;
wire app_wdf_afull;
wire app_af_afull;
wire rd_data_valid;
wire app_wdf_wren;
wire app_af_wren;
wire [30:0] app_af_addr;
wire [2:0] app_af_cmd;
wire [(APPDATA_WIDTH)-1:0] rd_data_fifo_out;
wire [(APPDATA_WIDTH)-1:0] app_wdf_data;
wire [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data;
// Debug signals (optional use)
wire dbg_idel_up_all;
wire dbg_idel_down_all;
wire dbg_idel_up_dq;
wire dbg_idel_down_dq;
wire dbg_idel_up_dqs;
wire dbg_idel_down_dqs;
wire dbg_idel_up_gate;
wire dbg_idel_down_gate;
wire [DQ_BITS-1:0] dbg_sel_idel_dq;
wire dbg_sel_all_idel_dq;
wire [DQS_BITS:0] dbg_sel_idel_dqs;
wire dbg_sel_all_idel_dqs;
wire [DQS_BITS:0] dbg_sel_idel_gate;
wire dbg_sel_all_idel_gate;
wire [3:0] dbg_calib_done;
wire [3:0] dbg_calib_err;
wire [(6*DQ_WIDTH)-1:0] dbg_calib_dq_tap_cnt;
wire [(6*DQS_WIDTH)-1:0] dbg_calib_dqs_tap_cnt;
wire [(6*DQS_WIDTH)-1:0] dbg_calib_gate_tap_cnt;
wire [DQS_WIDTH-1:0] dbg_calib_rd_data_sel;
wire [(5*DQS_WIDTH)-1:0] dbg_calib_rden_dly;
wire [(5*DQS_WIDTH)-1:0] dbg_calib_gate_dly;
//***********************************
// PHY Debug Port demo
//***********************************
wire [35:0] cs_control0;
wire [35:0] cs_control1;
wire [35:0] cs_control2;
wire [35:0] cs_control3;
wire [191:0] vio0_in;
wire [95:0] vio1_in;
wire [99:0] vio2_in;
wire [31:0] vio3_out;
// synthesis attribute X_CORE_INFO of ddr2_sdram is "mig_v2_1_ddr2_v5, Coregen 10.1i_ip0";
// synthesis attribute CORE_GENERATION_INFO of ddr2_sdram is "ddr2_v5,mig_v2_1,{component_name=ddr2_v5, bank_width=2, cke_width=1, clk_width=1, col_width=9, cs_num=1, cs_width=1, dm_width=2, dq_width=16, dq_per_dqs=8, dqs_width=2, odt_width=1, row_width=13, additive_lat=0, burst_len=4, burst_type=0, cas_lat=5, ecc_enable=0, multi_bank_en=1, two_t_time_en=0, odt_type=1, reduce_drv=0, reg_enable=0, trefi_ns=7800, tras=40000, trcd=15000, trfc=75000, trp=15000, trtp=7500, twr=15000, twtr=7500, clk_period=3333, rst_act_low=1}";
//***************************************************************************
idelay_ctrl u_idelay_ctrl
(
.rst200 (rst200),
.clk200 (clk200),
.idelay_ctrl_rdy (idelay_ctrl_rdy)
);
infrastructure #
(
.CLK_PERIOD (CLK_PERIOD),
.RST_ACT_LOW (RST_ACT_LOW),
.DLL_FREQ_MODE (DLL_FREQ_MODE)
)
u_infrastructure
(
.sys_clk_p (sys_clk_p),
.sys_clk_n (sys_clk_n),
.clk200_p (clk200_p),
.clk200_n (clk200_n),
.sys_rst_n (sys_rst_n),
.rst0 (rst0),
.rst90 (rst90),
.rst200 (rst200),
.rstdiv0 (rstdiv0),
.clk0 (clk0),
.clk90 (clk90),
.clk200 (clk200),
.clkdiv0 (clkdiv0),
.idelay_ctrl_rdy (idelay_ctrl_rdy)
);
ddr2_top #
(
.BANK_WIDTH (BANK_WIDTH),
.CKE_WIDTH (CKE_WIDTH),
.CLK_WIDTH (CLK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_NUM (CS_NUM),
.CS_WIDTH (CS_WIDTH),
.CS_BITS (CS_BITS),
.DM_WIDTH (DM_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQ_PER_DQS (DQ_PER_DQS),
.DQS_WIDTH (DQS_WIDTH),
.DQ_BITS (DQ_BITS),
.DQS_BITS (DQS_BITS),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.ADDITIVE_LAT (ADDITIVE_LAT),
.BURST_LEN (BURST_LEN),
.BURST_TYPE (BURST_TYPE),
.CAS_LAT (CAS_LAT),
.ECC_ENABLE (ECC_ENABLE),
.APPDATA_WIDTH (APPDATA_WIDTH),
.MULTI_BANK_EN (MULTI_BANK_EN),
.TWO_T_TIME_EN (TWO_T_TIME_EN),
.ODT_TYPE (ODT_TYPE),
.REDUCE_DRV (REDUCE_DRV),
.REG_ENABLE (REG_ENABLE),
.TREFI_NS (TREFI_NS),
.TRAS (TRAS),
.TRCD (TRCD),
.TRFC (TRFC),
.TRP (TRP),
.TRTP (TRTP),
.TWR (TWR),
.TWTR (TWTR),
.SIM_ONLY (SIM_ONLY),
.DEBUG_EN (DEBUG_EN),
.DQS_IO_COL (DQS_IO_COL),
.DQ_IO_MS (DQ_IO_MS),
.CLK_PERIOD (CLK_PERIOD)
)
u_ddr2_top
(
.ddr2_dq (ddr2_dq),
.ddr2_a (ddr2_a),
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