dtsm.vhd

在maxplus2环境下的vhdl设计交通灯

LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_unsigned.ALL; 
ENTITY dtsm IS
	PORT(clk:in STD_LOGIC;
 		 NumA,NumB,NumC,NumD: in STD_LOGIC_VECTOR(3 downto 0);
		 segout1:out STD_LOGIC_VECTOR(6 downto 0);
		 led_sel: out STD_LOGIC_VECTOR(3 downto 0));
END ENTITY dtsm;

architecture bhv of dtsm is
component bcd_data is 
	port (bcd_data:in STD_LOGIC_VECTOR(3 downto 0);
      	  segout:out STD_LOGIC_VECTOR(6 downto 0));
end component;
 signal x:STD_LOGIC_VECTOR(3 downto 0);
 signal q:STD_LOGIC_VECTOR(1 downto 0);
begin
p1:process(clk)
	begin
		if clk'event and clk ='1' then
 			Q<= Q + '1';
		end if;
end process;

p2:process(Q)
 begin
 case Q is
	when"00"=>led_sel<="1110";x<=NumD;
	when"01"=>led_sel<="1101";x<=NumC;
	when"10"=>led_sel<="1011";x<=NumB;
	when"11"=>led_sel<="0111";x<=NumA;
	when others=>null;
 end case;
end process;
 u1:bcd_data PORT map(bcd_data=>x,segout=>segout1);
end architecture bhv;