fenwei.rpt

在maxplus2环境下的vhdl设计交通灯

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Device-Specific Information:                                f:\jtd2\fenwei.rpt
fenwei

** EQUATIONS **

Numin0   : INPUT;
Numin1   : INPUT;
Numin2   : INPUT;
Numin3   : INPUT;
Numin4   : INPUT;
Numin5   : INPUT;
Numin6   : INPUT;

-- Node name is 'NumA0' 
-- Equation name is 'NumA0', type is output 
NumA0    = !_LC7_C24;

-- Node name is 'NumA1' 
-- Equation name is 'NumA1', type is output 
NumA1    =  _LC2_C16;

-- Node name is 'NumA2' 
-- Equation name is 'NumA2', type is output 
NumA2    =  _LC5_C16;

-- Node name is 'NumA3' 
-- Equation name is 'NumA3', type is output 
NumA3    =  GND;

-- Node name is 'NumB0~1' 
-- Equation name is 'NumB0~1', location is LC6_B3, type is buried.
-- synthesized logic cell 
_LC6_B3  = LCELL( Numin0);

-- Node name is 'NumB0' 
-- Equation name is 'NumB0', type is output 
NumB0    =  _LC6_B3;

-- Node name is 'NumB1' 
-- Equation name is 'NumB1', type is output 
NumB1    =  _LC1_C16;

-- Node name is 'NumB2' 
-- Equation name is 'NumB2', type is output 
NumB2    =  _LC4_C24;

-- Node name is 'NumB3' 
-- Equation name is 'NumB3', type is output 
NumB3    =  _LC2_C15;

-- Node name is '|LPM_ADD_SUB:531|addcore:adder|:125' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_C22', type is buried 
_LC1_C22 = LCELL( _EQ001);
  _EQ001 =  Numin1 &  Numin2;

-- Node name is ':129' 
-- Equation name is '_LC4_C22', type is buried 
_LC4_C22 = LCELL( _EQ002);
  _EQ002 = !Numin5 & !Numin6
         # !Numin2 & !Numin6
         # !_LC6_C22 & !Numin6;

-- Node name is ':172' 
-- Equation name is '_LC4_C16', type is buried 
!_LC4_C16 = _LC4_C16~NOT;
_LC4_C16~NOT = LCELL( _EQ003);
  _EQ003 = !_LC6_C16 &  Numin4 &  Numin5
         #  Numin1 &  Numin4 &  Numin5;

-- Node name is ':212' 
-- Equation name is '_LC3_C16', type is buried 
_LC3_C16 = LCELL( _EQ004);
  _EQ004 = !Numin3 & !Numin4
         # !Numin5;

-- Node name is ':249' 
-- Equation name is '_LC1_C15', type is buried 
!_LC1_C15 = _LC1_C15~NOT;
_LC1_C15~NOT = LCELL( _EQ005);
  _EQ005 =  _LC1_C22 &  Numin3 &  Numin4
         #  _LC2_C22;

-- Node name is '~257~1' 
-- Equation name is '~257~1', location is LC6_C22, type is buried.
-- synthesized logic cell 
!_LC6_C22 = _LC6_C22~NOT;
_LC6_C22~NOT = LCELL( _EQ006);
  _EQ006 = !Numin3
         # !Numin4;

-- Node name is ':297' 
-- Equation name is '_LC5_C22', type is buried 
_LC5_C22 = LCELL( _EQ007);
  _EQ007 = !Numin2 & !Numin3
         # !Numin4;

-- Node name is ':299' 
-- Equation name is '_LC6_C16', type is buried 
!_LC6_C16 = _LC6_C16~NOT;
_LC6_C16~NOT = LCELL( _EQ008);
  _EQ008 =  Numin2
         #  Numin3;

-- Node name is '~329~1' 
-- Equation name is '~329~1', location is LC2_C22, type is buried.
-- synthesized logic cell 
_LC2_C22 = LCELL( _EQ009);
  _EQ009 =  Numin6
         #  Numin5;

-- Node name is ':329' 
-- Equation name is '_LC4_C15', type is buried 
!_LC4_C15 = _LC4_C15~NOT;
_LC4_C15~NOT = LCELL( _EQ010);
  _EQ010 = !_LC3_C22 &  Numin3
         #  _LC2_C22
         #  Numin4;

-- Node name is ':344' 
-- Equation name is '_LC3_C22', type is buried 
!_LC3_C22 = _LC3_C22~NOT;
_LC3_C22~NOT = LCELL( _EQ011);
  _EQ011 =  Numin1
         #  Numin2;

-- Node name is '~740~1' 
-- Equation name is '~740~1', location is LC8_C16, type is buried.
-- synthesized logic cell 
!_LC8_C16 = _LC8_C16~NOT;
_LC8_C16~NOT = LCELL( _EQ012);
  _EQ012 =  _LC3_C16 &  _LC4_C16;

-- Node name is ':740' 
-- Equation name is '_LC5_C16', type is buried 
_LC5_C16 = LCELL( _EQ013);
  _EQ013 = !_LC4_C16
         # !_LC3_C16
         # !_LC4_C22;

-- Node name is ':761' 
-- Equation name is '_LC2_C16', type is buried 
_LC2_C16 = LCELL( _EQ014);
  _EQ014 = !_LC5_C22 & !_LC8_C16
         # !_LC1_C15 & !_LC8_C16
         # !_LC4_C22;

-- Node name is ':788' 
-- Equation name is '_LC3_C15', type is buried 
_LC3_C15 = LCELL( _EQ015);
  _EQ015 =  _LC2_C22 & !_LC3_C22 & !Numin3
         # !_LC3_C22 & !Numin3 &  Numin4
         #  _LC3_C22 &  Numin3;

-- Node name is ':791' 
-- Equation name is '_LC5_C15', type is buried 
_LC5_C15 = LCELL( _EQ016);
  _EQ016 =  _LC3_C15 &  _LC5_C22
         # !_LC5_C22 &  Numin2 &  Numin3
         # !_LC5_C22 & !Numin2 & !Numin3;

-- Node name is ':794' 
-- Equation name is '_LC6_C15', type is buried 
_LC6_C15 = LCELL( _EQ017);
  _EQ017 =  _LC1_C15 &  _LC5_C15
         # !_LC1_C15 &  _LC1_C22 & !Numin3
         # !_LC1_C15 & !_LC1_C22 &  Numin3;

-- Node name is ':797' 
-- Equation name is '_LC7_C15', type is buried 
_LC7_C15 = LCELL( _EQ018);
  _EQ018 =  _LC3_C16 &  _LC6_C15
         # !_LC3_C16 & !Numin3;

-- Node name is ':800' 
-- Equation name is '_LC8_C15', type is buried 
_LC8_C15 = LCELL( _EQ019);
  _EQ019 =  _LC4_C16 &  _LC7_C15
         # !_LC3_C22 & !_LC4_C16 &  Numin3
         #  _LC3_C22 & !_LC4_C16 & !Numin3;

-- Node name is ':803' 
-- Equation name is '_LC2_C15', type is buried 
_LC2_C15 = LCELL( _EQ020);
  _EQ020 =  _LC4_C22 &  _LC8_C15
         # !_LC4_C22 &  Numin2 & !Numin3
         # !_LC4_C22 & !Numin2 &  Numin3;

-- Node name is ':812' 
-- Equation name is '_LC3_C24', type is buried 
_LC3_C24 = LCELL( _EQ021);
  _EQ021 =  _LC5_C22 &  Numin1 &  Numin2
         # !_LC4_C15 & !Numin1 & !Numin2
         #  _LC4_C15 &  _LC5_C22 &  Numin2
         # !_LC5_C22 & !Numin2;

-- Node name is ':815' 
-- Equation name is '_LC5_C24', type is buried 
_LC5_C24 = LCELL( _EQ022);
  _EQ022 =  _LC1_C15 &  _LC3_C24
         # !_LC1_C15 &  Numin1 & !Numin2
         # !_LC1_C15 & !Numin1 &  Numin2;

-- Node name is ':818' 
-- Equation name is '_LC6_C24', type is buried 
_LC6_C24 = LCELL( _EQ023);
  _EQ023 =  _LC3_C16 &  _LC5_C24
         # !_LC3_C16 &  Numin2;

-- Node name is ':821' 
-- Equation name is '_LC8_C24', type is buried 
_LC8_C24 = LCELL( _EQ024);
  _EQ024 =  _LC4_C16 &  _LC6_C24
         # !_LC4_C16 &  Numin1 &  Numin2
         # !_LC4_C16 & !Numin1 & !Numin2;

-- Node name is ':824' 
-- Equation name is '_LC4_C24', type is buried 
_LC4_C24 = LCELL( _EQ025);
  _EQ025 =  _LC4_C22 &  _LC8_C24
         # !Numin2 &  Numin6;

-- Node name is '~845~1' 
-- Equation name is '~845~1', location is LC2_C24, type is buried.
-- synthesized logic cell 
!_LC2_C24 = _LC2_C24~NOT;
_LC2_C24~NOT = LCELL( _EQ026);
  _EQ026 = !_LC4_C15 &  _LC5_C22
         # !_LC1_C15;

-- Node name is '~845~2' 
-- Equation name is '~845~2', location is LC7_C24, type is buried.
-- synthesized logic cell 
!_LC7_C24 = _LC7_C24~NOT;
_LC7_C24~NOT = LCELL( _EQ027);
  _EQ027 = !_LC2_C24 &  _LC3_C16 &  _LC4_C22
         # !_LC4_C16 &  _LC4_C22;

-- Node name is '~845~3' 
-- Equation name is '~845~3', location is LC1_C24, type is buried.
-- synthesized logic cell 
_LC1_C24 = LCELL( _EQ028);
  _EQ028 =  _LC1_C15 & !_LC4_C15 &  _LC5_C22
         #  Numin5;

-- Node name is '~845~4' 
-- Equation name is '~845~4', location is LC7_C16, type is buried.
-- synthesized logic cell 
_LC7_C16 = LCELL( _EQ029);
  _EQ029 = !_LC4_C16
         #  _LC1_C24 &  _LC3_C16;

-- Node name is ':845' 
-- Equation name is '_LC1_C16', type is buried 
_LC1_C16 = LCELL( _EQ030);
  _EQ030 =  _LC7_C24 &  Numin1
         #  _LC4_C22 &  _LC7_C16 & !Numin1;



Project Information                                         f:\jtd2\fenwei.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 17,464K