📄 jtd.rpt
字号:
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: g:\jtd2\jtd.rpt
jtd
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - H 16 OR2 ! 0 2 0 5 |COUNTER:27|LPM_ADD_SUB:160|addcore:adder|:121
- 2 - H 15 AND2 0 3 0 3 |COUNTER:27|LPM_ADD_SUB:160|addcore:adder|:129
- 8 - H 15 AND2 0 2 0 10 |COUNTER:27|LPM_ADD_SUB:160|addcore:adder|:133
- 7 - H 26 AND2 0 2 0 1 |COUNTER:27|LPM_ADD_SUB:160|addcore:adder|:137
- 4 - H 19 OR2 0 3 0 2 |COUNTER:27|LPM_ADD_SUB:160|addcore:adder|:151
- 5 - H 26 DFFE 2 3 0 9 |COUNTER:27|:4
- 6 - H 26 DFFE 2 3 0 19 |COUNTER:27|:6
- 2 - H 10 DFFE 2 3 0 8 |COUNTER:27|:8
- 2 - H 19 DFFE 2 3 0 11 |COUNTER:27|:10
- 1 - H 26 DFFE 2 3 0 13 |COUNTER:27|:12
- 5 - H 17 DFFE 2 3 0 5 |COUNTER:27|:14
- 6 - H 17 DFFE 2 1 0 9 |COUNTER:27|:16
- 4 - H 26 OR2 s 0 2 0 1 |COUNTER:27|~109~1
- 3 - H 26 OR2 s 1 3 0 6 |COUNTER:27|~278~1
- 6 - H 10 AND2 ! 0 2 0 1 |COUNTROLLER:26|LPM_ADD_SUB:272|addcore:adder|pcarry3
- 4 - H 15 OR2 0 3 0 3 |COUNTROLLER:26|LPM_ADD_SUB:272|addcore:adder|pcarry4
- 8 - H 50 OR2 0 2 0 1 |COUNTROLLER:26|LPM_ADD_SUB:272|addcore:adder|:160
- 1 - H 16 AND2 0 2 0 3 |COUNTROLLER:26|LPM_ADD_SUB:329|addcore:adder|:121
- 8 - H 16 AND2 0 2 0 4 |COUNTROLLER:26|LPM_ADD_SUB:329|addcore:adder|:125
- 3 - H 15 AND2 0 3 0 4 |COUNTROLLER:26|LPM_ADD_SUB:329|addcore:adder|:133
- 2 - H 06 OR2 ! 0 2 0 3 |COUNTROLLER:26|LPM_ADD_SUB:386|addcore:adder|:129
- 1 - H 06 OR2 ! 0 2 0 4 |COUNTROLLER:26|LPM_ADD_SUB:386|addcore:adder|:133
- 4 - H 47 DFFE 1 3 0 4 |COUNTROLLER:26|:10
- 2 - H 35 DFFE 1 2 0 6 |COUNTROLLER:26|:12
- 1 - H 10 DFFE 1 2 0 7 |COUNTROLLER:26|:14
- 1 - H 19 DFFE 1 2 0 12 |COUNTROLLER:26|:16
- 3 - H 16 DFFE 1 2 0 13 |COUNTROLLER:26|:18
- 3 - H 17 DFFE 1 2 0 8 |COUNTROLLER:26|:20
- 2 - H 26 DFFE 1 2 1 0 |COUNTROLLER:26|:22
- 3 - H 50 DFFE 0 5 0 3 |COUNTROLLER:26|:24
- 4 - H 50 DFFE 0 5 0 5 |COUNTROLLER:26|:26
- 4 - H 10 DFFE 0 4 0 7 |COUNTROLLER:26|:28
- 3 - H 19 DFFE 0 5 0 12 |COUNTROLLER:26|:30
- 2 - H 16 DFFE 0 5 0 12 |COUNTROLLER:26|:32
- 2 - H 17 DFFE 0 5 0 7 |COUNTROLLER:26|:34
- 1 - H 17 DFFE 0 5 1 0 |COUNTROLLER:26|:36
- 3 - D 47 DFFE 1 2 1 0 |COUNTROLLER:26|:38
- 7 - H 50 DFFE 1 4 1 0 |COUNTROLLER:26|:40
- 6 - H 47 DFFE 1 3 1 0 |COUNTROLLER:26|:42
- 1 - D 47 DFFE 0 2 1 0 |COUNTROLLER:26|:44
- 5 - H 15 DFFE 0 4 1 0 |COUNTROLLER:26|:46
- 7 - H 15 DFFE 0 4 1 0 |COUNTROLLER:26|:48
- 6 - H 15 OR2 ! 0 3 0 8 |COUNTROLLER:26|:158
- 1 - H 15 OR2 ! 0 3 0 18 |COUNTROLLER:26|:200
- 1 - H 50 OR2 0 4 0 1 |COUNTROLLER:26|:423
- 6 - H 50 OR2 0 3 0 2 |COUNTROLLER:26|:442
- 5 - H 50 OR2 0 3 0 2 |COUNTROLLER:26|:443
- 2 - H 50 OR2 0 4 0 1 |COUNTROLLER:26|:444
- 5 - H 10 OR2 0 4 0 1 |COUNTROLLER:26|:453
- 3 - H 10 OR2 0 4 0 2 |COUNTROLLER:26|:454
- 7 - H 10 OR2 0 4 0 1 |COUNTROLLER:26|:456
- 5 - H 19 OR2 0 4 0 1 |COUNTROLLER:26|:465
- 6 - H 19 OR2 0 4 0 1 |COUNTROLLER:26|:468
- 4 - H 16 OR2 0 3 0 1 |COUNTROLLER:26|:478
- 5 - H 16 OR2 s 0 4 0 1 |COUNTROLLER:26|~483~1
- 4 - H 17 OR2 s 0 4 0 1 |COUNTROLLER:26|~495~1
- 8 - H 26 OR2 s 0 4 0 1 |COUNTROLLER:26|~507~1
- 8 - H 10 OR2 0 4 0 1 |COUNTROLLER:26|:863
- 8 - H 19 OR2 0 4 0 1 |COUNTROLLER:26|:872
- 7 - H 19 OR2 0 4 0 1 |COUNTROLLER:26|:874
- 6 - H 16 OR2 0 4 0 1 |COUNTROLLER:26|:881
- 8 - H 17 OR2 0 4 0 1 |COUNTROLLER:26|:890
- 7 - H 17 OR2 0 3 0 1 |COUNTROLLER:26|:899
- 2 - J 03 AND2 0 2 0 2 |FENWEI2:25|LPM_ADD_SUB:531|addcore:adder|:125
- 5 - J 20 OR2 0 4 0 6 |FENWEI2:25|:129
- 1 - J 20 OR2 ! 0 4 0 6 |FENWEI2:25|:172
- 4 - J 20 OR2 0 3 0 6 |FENWEI2:25|:212
- 1 - J 22 OR2 ! 0 4 0 5 |FENWEI2:25|:249
- 6 - J 20 OR2 s ! 0 2 0 1 |FENWEI2:25|~257~1
- 3 - J 20 OR2 0 3 0 5 |FENWEI2:25|:297
- 7 - J 20 OR2 ! 0 2 0 1 |FENWEI2:25|:299
- 2 - J 20 OR2 s 0 2 0 3 |FENWEI2:25|~329~1
- 3 - J 22 OR2 ! 0 4 0 3 |FENWEI2:25|:329
- 1 - J 03 OR2 ! 0 2 0 3 |FENWEI2:25|:344
- 1 - J 21 AND2 s ! 0 2 0 1 |FENWEI2:25|~740~1
- 2 - J 24 OR2 0 3 1 0 |FENWEI2:25|:740
- 2 - J 21 OR2 0 4 1 0 |FENWEI2:25|:761
- 4 - J 22 OR2 0 4 0 1 |FENWEI2:25|:788
- 5 - J 22 OR2 0 4 0 1 |FENWEI2:25|:791
- 6 - J 22 OR2 0 4 0 1 |FENWEI2:25|:794
- 7 - J 22 OR2 0 3 0 1 |FENWEI2:25|:797
- 8 - J 22 OR2 0 4 0 1 |FENWEI2:25|:800
- 2 - J 22 OR2 0 4 1 0 |FENWEI2:25|:803
- 5 - J 19 OR2 0 4 0 1 |FENWEI2:25|:812
- 6 - J 19 OR2 0 4 0 1 |FENWEI2:25|:815
- 7 - J 19 OR2 0 3 0 1 |FENWEI2:25|:818
- 2 - J 19 OR2 0 4 0 1 |FENWEI2:25|:821
- 8 - J 20 OR2 0 4 1 0 |FENWEI2:25|:824
- 1 - J 19 OR2 s ! 0 3 0 1 |FENWEI2:25|~845~1
- 4 - J 21 OR2 s ! 0 4 1 1 |FENWEI2:25|~845~2
- 3 - J 19 OR2 s 0 4 0 1 |FENWEI2:25|~845~3
- 4 - J 19 OR2 s 0 3 0 1 |FENWEI2:25|~845~4
- 8 - J 19 OR2 0 4 1 0 |FENWEI2:25|:845
- 1 - H 33 AND2 ! 0 2 0 3 |FENWEI:24|LPM_ADD_SUB:437|addcore:adder|pcarry2
- 5 - H 33 AND2 0 2 0 1 |FENWEI:24|LPM_ADD_SUB:531|addcore:adder|:125
- 4 - H 28 AND2 s 0 3 0 1 |FENWEI:24|~129~1
- 3 - H 47 OR2 ! 0 4 0 6 |FENWEI:24|:129
- 7 - H 47 OR2 s ! 0 2 0 2 |FENWEI:24|~132~1
- 2 - H 47 OR2 0 4 0 6 |FENWEI:24|:172
- 7 - H 35 OR2 ! 0 3 0 5 |FENWEI:24|:212
- 5 - H 47 OR2 0 4 0 5 |FENWEI:24|:249
- 1 - H 35 OR2 s ! 0 3 0 1 |FENWEI:24|~257~1
- 5 - H 35 OR2 ! 0 3 0 4 |FENWEI:24|:297
- 1 - H 47 AND2 0 4 0 4 |FENWEI:24|:329
- 8 - H 47 OR2 0 2 0 1 |FENWEI:24|:342
- 3 - H 35 AND2 s ! 0 2 0 1 |FENWEI:24|~740~1
- 4 - H 37 OR2 0 3 1 0 |FENWEI:24|:740
- 1 - H 37 OR2 0 4 1 0 |FENWEI:24|:761
- 3 - H 28 OR2 ! 0 3 0 1 |FENWEI:24|:773
- 4 - H 35 OR2 ! 0 4 1 1 |FENWEI:24|:784
- 3 - H 33 OR2 0 3 0 1 |FENWEI:24|:788
- 4 - H 33 OR2 0 4 0 1 |FENWEI:24|:791
- 6 - H 33 OR2 0 4 0 1 |FENWEI:24|:794
- 7 - H 33 OR2 0 4 0 1 |FENWEI:24|:797
- 8 - H 33 OR2 0 4 0 1 |FENWEI:24|:800
- 2 - H 33 OR2 0 4 1 0 |FENWEI:24|:803
- 6 - H 28 OR2 0 4 0 1 |FENWEI:24|:812
- 7 - H 28 OR2 0 4 0 1 |FENWEI:24|:815
- 8 - H 28 OR2 0 3 0 1 |FENWEI:24|:818
- 1 - H 28 OR2 0 4 0 1 |FENWEI:24|:821
- 4 - H 29 OR2 0 4 1 0 |FENWEI:24|:824
- 5 - H 28 OR2 s 0 4 0 1 |FENWEI:24|~845~1
- 2 - H 28 OR2 0 4 1 0 |FENWEI:24|:845
- 6 - D 51 AND2 0 3 0 1 |FREDEVIDER:5|LPM_ADD_SUB:121|addcore:adder|:83
- 3 - D 51 AND2 0 4 0 3 |FREDEVIDER:5|LPM_ADD_SUB:121|addcore:adder|:87
- 2 - D 51 AND2 0 3 0 3 |FREDEVIDER:5|LPM_ADD_SUB:121|addcore:adder|:95
- 5 - D 47 AND2 0 2 0 1 |FREDEVIDER:5|LPM_ADD_SUB:121|addcore:adder|:99
- 8 - D 47 DFFE + 0 3 0 1 |FREDEVIDER:5|counter8 (|FREDEVIDER:5|:3)
- 4 - D 47 DFFE + 0 3 0 2 |FREDEVIDER:5|counter7 (|FREDEVIDER:5|:4)
- 2 - D 47 DFFE + 0 2 0 3 |FREDEVIDER:5|counter6 (|FREDEVIDER:5|:5)
- 5 - D 51 DFFE + 0 3 0 2 |FREDEVIDER:5|counter5 (|FREDEVIDER:5|:6)
- 8 - D 51 DFFE + 0 2 0 3 |FREDEVIDER:5|counter4 (|FREDEVIDER:5|:7)
- 7 - D 51 DFFE + 0 2 0 2 |FREDEVIDER:5|counter3 (|FREDEVIDER:5|:8)
- 2 - D 40 DFFE + 0 3 0 3 |FREDEVIDER:5|counter2 (|FREDEVIDER:5|:9)
- 1 - D 40 DFFE + 0 2 0 4 |FREDEVIDER:5|counter1 (|FREDEVIDER:5|:10)
- 3 - D 40 DFFE + 0 0 0 5 |FREDEVIDER:5|counter0 (|FREDEVIDER:5|:11)
- 6 - D 47 DFFE + 0 1 0 27 |FREDEVIDER:5|Clk (|FREDEVIDER:5|:12)
- 7 - D 47 OR2 s 0 3 0 1 |FREDEVIDER:5|~50~1
- 4 - D 51 OR2 s 0 4 0 1 |FREDEVIDER:5|~50~2
- 1 - D 51 OR2 ! 0 4 0 9 |FREDEVIDER:5|:50
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: g:\jtd2\jtd.rpt
jtd
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 9/208( 4%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
E: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 33/208( 15%) 1/104( 0%) 12/104( 11%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
I: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
J: 3/208( 1%) 15/104( 14%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
K: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
L: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
19: 3/24( 12%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
25: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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